diff --git a/ports/risc-v64/gnu/inc/tx_port.h b/ports/risc-v64/gnu/inc/tx_port.h
index 0e31cc426..ad71694be 100644
--- a/ports/risc-v64/gnu/inc/tx_port.h
+++ b/ports/risc-v64/gnu/inc/tx_port.h
@@ -84,6 +84,11 @@
 #define TX_RISCV_TRAP_FRAME_SIZE                256
 #endif
 
+/* Bytes a trap entry reserves around a call into C.  The RISC-V psABI
+   requires sp to stay 16-byte aligned at a call boundary, so this is 16
+   rather than one register slot.  */
+#define TX_RISCV_TRAP_CALL_FRAME_SIZE           16
+
 
 #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
 #define TX_RISCV_SOL_FRAME_SIZE                 240
diff --git a/test/tx/cmake/riscv/bsp/tx_initialize_low_level.S b/test/tx/cmake/riscv/bsp/tx_initialize_low_level.S
index 8d474d66b..327946bb0 100644
--- a/test/tx/cmake/riscv/bsp/tx_initialize_low_level.S
+++ b/test/tx/cmake/riscv/bsp/tx_initialize_low_level.S
@@ -1,5 +1,6 @@
 /***************************************************************************
  * Copyright (c) 2026 10xEngineers
+ * Copyright (c) 2026 Eclipse ThreadX contributors
  *
  * This program and the accompanying materials are made available under the
  * terms of the MIT License which is available at
@@ -8,10 +9,13 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Claude Code (Opus 5).
+
 /* Trap entry and low-level init for RISC-V QEMU virt regression tests.
    Supports both RV32 and RV64 via __riscv_xlen conditionals. */
 
 #include "csr.h"
+#include "tx_port.h"
 
 #if __riscv_xlen == 64
 #define STORE   sd
@@ -33,13 +37,28 @@
     .extern  trap_handler
     .extern  _tx_thread_context_restore
 
-trap_entry:
+/* Take the interrupt frame size from the port that this BSP is linked
+   against, so the two can never disagree.  A port that publishes no
+   contract keeps the historical layout.  */
+#ifndef TX_RISCV_TRAP_FRAME_SIZE
 #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
-    addi    sp, sp, -(65 * REGBYTES)
+#define TX_RISCV_TRAP_FRAME_SIZE        (65 * REGBYTES)
 #else
-    addi    sp, sp, -(32 * REGBYTES)
+#define TX_RISCV_TRAP_FRAME_SIZE        (32 * REGBYTES)
+#endif
+#endif
+
+/* The RISC-V psABI requires sp to be 16-byte aligned at a call.  */
+#ifndef TX_RISCV_TRAP_CALL_FRAME_SIZE
+#define TX_RISCV_TRAP_CALL_FRAME_SIZE   16
 #endif
 
+    .equ    TX_TRAP_FRAME_SIZE, TX_RISCV_TRAP_FRAME_SIZE
+    .equ    TX_TRAP_CALL_FRAME_SIZE, TX_RISCV_TRAP_CALL_FRAME_SIZE
+
+trap_entry:
+    addi    sp, sp, -TX_TRAP_FRAME_SIZE
+
     STORE   x1, (28 * REGBYTES)(sp)
 
     call    _tx_thread_context_save
@@ -47,11 +66,11 @@ trap_entry:
     csrr    a0, mcause
     csrr    a1, mepc
     csrr    a2, mtval
-    addi    sp, sp, -REGBYTES
+    addi    sp, sp, -TX_TRAP_CALL_FRAME_SIZE
     STORE   ra, 0(sp)
     call    trap_handler
     LOAD    ra, 0(sp)
-    addi    sp, sp, REGBYTES
+    addi    sp, sp, TX_TRAP_CALL_FRAME_SIZE
 
     call    _tx_thread_context_restore
 
@@ -89,11 +108,11 @@ _tx_initialize_low_level:
     fscsr   x0
 #endif
 
-    addi    sp, sp, -REGBYTES
+    addi    sp, sp, -TX_TRAP_CALL_FRAME_SIZE
     STORE   ra, 0(sp)
     call    board_init
     LOAD    ra, 0(sp)
-    addi    sp, sp, REGBYTES
+    addi    sp, sp, TX_TRAP_CALL_FRAME_SIZE
 
     la      t0, trap_entry
     csrw    mtvec, t0