From 964ad8c9691ce46a7cd21980f058a311e7953142 Mon Sep 17 00:00:00 2001
From: TechnoPorg <mail@technop.org>
Date: Thu, 8 Oct 2026 15:56:14 -0400
Subject: [PATCH 1/6] Make RISC-V bit manip intrinsics use u32/u64 instead of
 usize

---
 crates/core_arch/src/riscv32/mod.rs      |   4 +
 crates/core_arch/src/riscv32/zb.rs       | 132 ++++++++++++++++++++++
 crates/core_arch/src/riscv64/mod.rs      |   4 +
 crates/core_arch/src/riscv64/zb.rs       | 132 ++++++++++++++++++++++
 crates/core_arch/src/riscv_shared/mod.rs |   3 -
 crates/core_arch/src/riscv_shared/zb.rs  | 134 -----------------------
 crates/core_arch/src/riscv_shared/zk.rs  |  74 -------------
 7 files changed, 272 insertions(+), 211 deletions(-)
 create mode 100644 crates/core_arch/src/riscv32/zb.rs
 create mode 100644 crates/core_arch/src/riscv64/zb.rs
 delete mode 100644 crates/core_arch/src/riscv_shared/zb.rs

diff --git a/crates/core_arch/src/riscv32/mod.rs b/crates/core_arch/src/riscv32/mod.rs
index 7ff871227b..7017b7edc4 100644
--- a/crates/core_arch/src/riscv32/mod.rs
+++ b/crates/core_arch/src/riscv32/mod.rs
@@ -1,6 +1,10 @@
 //! RISC-V RV32 specific intrinsics
 
+mod zb;
 mod zk;
 
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+pub use zb::*;
+
 #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub use zk::*;
diff --git a/crates/core_arch/src/riscv32/zb.rs b/crates/core_arch/src/riscv32/zb.rs
new file mode 100644
index 0000000000..ccde8134b8
--- /dev/null
+++ b/crates/core_arch/src/riscv32/zb.rs
@@ -0,0 +1,132 @@
+#[cfg(test)]
+use stdarch_test::assert_instr;
+
+unsafe extern "llvm-intrinsic" {
+    #[link_name = "llvm.riscv.xperm8.i32"]
+    fn _xperm8(rs1: i32, rs2: i32) -> i32;
+
+    #[link_name = "llvm.riscv.xperm4.i32"]
+    fn _xperm4(rs1: i32, rs2: i32) -> i32;
+
+    #[link_name = "llvm.riscv.orc.b.i32"]
+    fn _orc_b(rs: i32) -> i32;
+
+    #[link_name = "llvm.riscv.clmul.i32"]
+    fn _clmul(rs1: i32, rs2: i32) -> i32;
+
+    #[link_name = "llvm.riscv.clmulh.i32"]
+    fn _clmulh(rs1: i32, rs2: i32) -> i32;
+
+    #[link_name = "llvm.riscv.clmulr.i32"]
+    fn _clmulr(rs1: i32, rs2: i32) -> i32;
+}
+
+/// Byte-wise lookup of indices into a vector in registers.
+///
+/// The xperm8 instruction operates on bytes. The rs1 register contains a vector of XLEN/8
+/// 8-bit elements. The rs2 register contains a vector of XLEN/8 8-bit indexes. The result is
+/// each element in rs2 replaced by the indexed element in rs1, or zero if the index into rs2
+/// is out of bounds.
+///
+/// Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions
+///
+/// Version: v1.0.1
+///
+/// Section: 3.47
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[target_feature(enable = "zbkx")]
+#[cfg_attr(test, assert_instr(xperm8))]
+#[inline]
+pub fn xperm8(rs1: u32, rs2: u32) -> u32 {
+    unsafe { _xperm8(rs1 as i32, rs2 as i32) as u32 }
+}
+
+/// Nibble-wise lookup of indices into a vector.
+///
+/// The xperm4 instruction operates on nibbles. The rs1 register contains a vector of XLEN/4
+/// 4-bit elements. The rs2 register contains a vector of XLEN/4 4-bit indexes. The result is
+/// each element in rs2 replaced by the indexed element in rs1, or zero if the index into rs2
+/// is out of bounds.
+///
+/// Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions
+///
+/// Version: v1.0.1
+///
+/// Section: 3.48
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[target_feature(enable = "zbkx")]
+#[cfg_attr(test, assert_instr(xperm4))]
+#[inline]
+pub fn xperm4(rs1: u32, rs2: u32) -> u32 {
+    unsafe { _xperm4(rs1 as i32, rs2 as i32) as u32 }
+}
+
+/// Bitwise OR-Combine, byte granule
+///
+/// Combines the bits within every byte through a reciprocal bitwise logical OR. This sets the bits of each byte in
+/// the result rd to all zeros if no bit within the respective byte of rs is set, or to all ones if any bit within the
+/// respective byte of rs is set.
+///
+/// Source: RISC-V Bit-Manipulation ISA-extensions
+///
+/// Version: v1.0.0
+///
+/// Section: 2.24
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[target_feature(enable = "zbb")]
+#[cfg_attr(test, assert_instr(orc.b))]
+#[inline]
+pub fn orc_b(rs: u32) -> u32 {
+    unsafe { _orc_b(rs as i32) as u32 }
+}
+
+/// Carry-less multiply (low-part)
+///
+/// clmul produces the lower half of the 2·XLEN carry-less product.
+///
+/// Source: RISC-V Bit-Manipulation ISA-extensions
+///
+/// Version: v1.0.0
+///
+/// Section: 2.11
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[target_feature(enable = "zbkc")]
+#[cfg_attr(test, assert_instr(clmul))]
+#[inline]
+pub fn clmul(rs1: u32, rs2: u32) -> u32 {
+    unsafe { _clmul(rs1 as i32, rs2 as i32) as u32 }
+}
+
+/// Carry-less multiply (high-part)
+///
+/// clmulh produces the upper half of the 2·XLEN carry-less product.
+///
+/// Source: RISC-V Bit-Manipulation ISA-extensions
+///
+/// Version: v1.0.0
+///
+/// Section: 2.12
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[target_feature(enable = "zbkc")]
+#[cfg_attr(test, assert_instr(clmulh))]
+#[inline]
+pub fn clmulh(rs1: u32, rs2: u32) -> u32 {
+    unsafe { _clmulh(rs1 as i32, rs2 as i32) as u32 }
+}
+
+/// Carry-less multiply (reversed)
+///
+/// clmulr produces bits 2·XLEN−2:XLEN-1 of the 2·XLEN carry-less product.
+///
+/// Source: RISC-V Bit-Manipulation ISA-extensions
+///
+/// Version: v1.0.0
+///
+/// Section: 2.13
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[target_feature(enable = "zbc")]
+#[cfg_attr(test, assert_instr(clmulr))]
+#[inline]
+pub fn clmulr(rs1: u32, rs2: u32) -> u32 {
+    unsafe { _clmulr(rs1 as i32, rs2 as i32) as u32 }
+}
diff --git a/crates/core_arch/src/riscv64/mod.rs b/crates/core_arch/src/riscv64/mod.rs
index a7efc0c7f5..8301ea2b23 100644
--- a/crates/core_arch/src/riscv64/mod.rs
+++ b/crates/core_arch/src/riscv64/mod.rs
@@ -1,8 +1,12 @@
 //! RISC-V RV64 specific intrinsics
 use crate::arch::asm;
 
+mod zb;
 mod zk;
 
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+pub use zb::*;
+
 #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub use zk::*;
 
diff --git a/crates/core_arch/src/riscv64/zb.rs b/crates/core_arch/src/riscv64/zb.rs
new file mode 100644
index 0000000000..9e1ac328bc
--- /dev/null
+++ b/crates/core_arch/src/riscv64/zb.rs
@@ -0,0 +1,132 @@
+#[cfg(test)]
+use stdarch_test::assert_instr;
+
+unsafe extern "llvm-intrinsic" {
+    #[link_name = "llvm.riscv.xperm8.i64"]
+    fn _xperm8(rs1: i64, rs2: i64) -> i64;
+
+    #[link_name = "llvm.riscv.xperm4.i64"]
+    fn _xperm4(rs1: i64, rs2: i64) -> i64;
+
+    #[link_name = "llvm.riscv.orc.b.i64"]
+    fn _orc_b(rs: i64) -> i64;
+
+    #[link_name = "llvm.riscv.clmul.i64"]
+    fn _clmul(rs1: i64, rs2: i64) -> i64;
+
+    #[link_name = "llvm.riscv.clmulh.i64"]
+    fn _clmulh(rs1: i64, rs2: i64) -> i64;
+
+    #[link_name = "llvm.riscv.clmulr.i64"]
+    fn _clmulr(rs1: i64, rs2: i64) -> i64;
+}
+
+/// Byte-wise lookup of indices into a vector in registers.
+///
+/// The xperm8 instruction operates on bytes. The rs1 register contains a vector of XLEN/8
+/// 8-bit elements. The rs2 register contains a vector of XLEN/8 8-bit indexes. The result is
+/// each element in rs2 replaced by the indexed element in rs1, or zero if the index into rs2
+/// is out of bounds.
+///
+/// Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions
+///
+/// Version: v1.0.1
+///
+/// Section: 3.47
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[target_feature(enable = "zbkx")]
+#[cfg_attr(test, assert_instr(xperm8))]
+#[inline]
+pub fn xperm8(rs1: u64, rs2: u64) -> u64 {
+    unsafe { _xperm8(rs1 as i64, rs2 as i64) as u64 }
+}
+
+/// Nibble-wise lookup of indices into a vector.
+///
+/// The xperm4 instruction operates on nibbles. The rs1 register contains a vector of XLEN/4
+/// 4-bit elements. The rs2 register contains a vector of XLEN/4 4-bit indexes. The result is
+/// each element in rs2 replaced by the indexed element in rs1, or zero if the index into rs2
+/// is out of bounds.
+///
+/// Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions
+///
+/// Version: v1.0.1
+///
+/// Section: 3.48
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[target_feature(enable = "zbkx")]
+#[cfg_attr(test, assert_instr(xperm4))]
+#[inline]
+pub fn xperm4(rs1: u64, rs2: u64) -> u64 {
+    unsafe { _xperm4(rs1 as i64, rs2 as i64) as u64 }
+}
+
+/// Bitwise OR-Combine, byte granule
+///
+/// Combines the bits within every byte through a reciprocal bitwise logical OR. This sets the bits of each byte in
+/// the result rd to all zeros if no bit within the respective byte of rs is set, or to all ones if any bit within the
+/// respective byte of rs is set.
+///
+/// Source: RISC-V Bit-Manipulation ISA-extensions
+///
+/// Version: v1.0.0
+///
+/// Section: 2.24
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[target_feature(enable = "zbb")]
+#[cfg_attr(test, assert_instr(orc.b))]
+#[inline]
+pub fn orc_b(rs: u64) -> u64 {
+    unsafe { _orc_b(rs as i64) as u64 }
+}
+
+/// Carry-less multiply (low-part)
+///
+/// clmul produces the lower half of the 2·XLEN carry-less product.
+///
+/// Source: RISC-V Bit-Manipulation ISA-extensions
+///
+/// Version: v1.0.0
+///
+/// Section: 2.11
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[target_feature(enable = "zbkc")]
+#[cfg_attr(test, assert_instr(clmul))]
+#[inline]
+pub fn clmul(rs1: u64, rs2: u64) -> u64 {
+    unsafe { _clmul(rs1 as i64, rs2 as i64) as u64 }
+}
+
+/// Carry-less multiply (high-part)
+///
+/// clmulh produces the upper half of the 2·XLEN carry-less product.
+///
+/// Source: RISC-V Bit-Manipulation ISA-extensions
+///
+/// Version: v1.0.0
+///
+/// Section: 2.12
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[target_feature(enable = "zbkc")]
+#[cfg_attr(test, assert_instr(clmulh))]
+#[inline]
+pub fn clmulh(rs1: u64, rs2: u64) -> u64 {
+    unsafe { _clmulh(rs1 as i64, rs2 as i64) as u64 }
+}
+
+/// Carry-less multiply (reversed)
+///
+/// clmulr produces bits 2·XLEN−2:XLEN-1 of the 2·XLEN carry-less product.
+///
+/// Source: RISC-V Bit-Manipulation ISA-extensions
+///
+/// Version: v1.0.0
+///
+/// Section: 2.13
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[target_feature(enable = "zbc")]
+#[cfg_attr(test, assert_instr(clmulr))]
+#[inline]
+pub fn clmulr(rs1: u64, rs2: u64) -> u64 {
+    unsafe { _clmulr(rs1 as i64, rs2 as i64) as u64 }
+}
diff --git a/crates/core_arch/src/riscv_shared/mod.rs b/crates/core_arch/src/riscv_shared/mod.rs
index f3933f58b1..bb6549f8e1 100644
--- a/crates/core_arch/src/riscv_shared/mod.rs
+++ b/crates/core_arch/src/riscv_shared/mod.rs
@@ -25,14 +25,11 @@
 //! single inline assembly block and make sure to restore the original rounding mode before the end
 //! of the block.
 mod p;
-mod zb;
 mod zk;
 
 #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub use p::*;
 #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
-pub use zb::*;
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub use zk::*;
 
 use crate::arch::asm;
diff --git a/crates/core_arch/src/riscv_shared/zb.rs b/crates/core_arch/src/riscv_shared/zb.rs
deleted file mode 100644
index 79ffe2af33..0000000000
--- a/crates/core_arch/src/riscv_shared/zb.rs
+++ /dev/null
@@ -1,134 +0,0 @@
-#[cfg(test)]
-use stdarch_test::assert_instr;
-
-#[cfg(target_arch = "riscv32")]
-unsafe extern "llvm-intrinsic" {
-    #[link_name = "llvm.riscv.orc.b.i32"]
-    fn _orc_b_32(rs: i32) -> i32;
-
-    #[link_name = "llvm.riscv.clmul.i32"]
-    fn _clmul_32(rs1: i32, rs2: i32) -> i32;
-
-    #[link_name = "llvm.riscv.clmulh.i32"]
-    fn _clmulh_32(rs1: i32, rs2: i32) -> i32;
-
-    #[link_name = "llvm.riscv.clmulr.i32"]
-    fn _clmulr_32(rs1: i32, rs2: i32) -> i32;
-}
-
-#[cfg(target_arch = "riscv64")]
-unsafe extern "llvm-intrinsic" {
-    #[link_name = "llvm.riscv.orc.b.i64"]
-    fn _orc_b_64(rs1: i64) -> i64;
-
-    #[link_name = "llvm.riscv.clmul.i64"]
-    fn _clmul_64(rs1: i64, rs2: i64) -> i64;
-
-    #[link_name = "llvm.riscv.clmulh.i64"]
-    fn _clmulh_64(rs1: i64, rs2: i64) -> i64;
-
-    #[link_name = "llvm.riscv.clmulr.i64"]
-    fn _clmulr_64(rs1: i64, rs2: i64) -> i64;
-}
-
-/// Bitwise OR-Combine, byte granule
-///
-/// Combines the bits within every byte through a reciprocal bitwise logical OR. This sets the bits of each byte in
-/// the result rd to all zeros if no bit within the respective byte of rs is set, or to all ones if any bit within the
-/// respective byte of rs is set.
-///
-/// Source: RISC-V Bit-Manipulation ISA-extensions
-///
-/// Version: v1.0.0
-///
-/// Section: 2.24
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
-#[target_feature(enable = "zbb")]
-#[cfg_attr(test, assert_instr(orc.b))]
-#[inline]
-pub fn orc_b(rs: usize) -> usize {
-    #[cfg(target_arch = "riscv32")]
-    unsafe {
-        _orc_b_32(rs as i32) as usize
-    }
-
-    #[cfg(target_arch = "riscv64")]
-    unsafe {
-        _orc_b_64(rs as i64) as usize
-    }
-}
-
-/// Carry-less multiply (low-part)
-///
-/// clmul produces the lower half of the 2·XLEN carry-less product.
-///
-/// Source: RISC-V Bit-Manipulation ISA-extensions
-///
-/// Version: v1.0.0
-///
-/// Section: 2.11
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
-#[target_feature(enable = "zbkc")]
-#[cfg_attr(test, assert_instr(clmul))]
-#[inline]
-pub fn clmul(rs1: usize, rs2: usize) -> usize {
-    #[cfg(target_arch = "riscv32")]
-    unsafe {
-        _clmul_32(rs1 as i32, rs2 as i32) as usize
-    }
-
-    #[cfg(target_arch = "riscv64")]
-    unsafe {
-        _clmul_64(rs1 as i64, rs2 as i64) as usize
-    }
-}
-
-/// Carry-less multiply (high-part)
-///
-/// clmulh produces the upper half of the 2·XLEN carry-less product.
-///
-/// Source: RISC-V Bit-Manipulation ISA-extensions
-///
-/// Version: v1.0.0
-///
-/// Section: 2.12
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
-#[target_feature(enable = "zbkc")]
-#[cfg_attr(test, assert_instr(clmulh))]
-#[inline]
-pub fn clmulh(rs1: usize, rs2: usize) -> usize {
-    #[cfg(target_arch = "riscv32")]
-    unsafe {
-        _clmulh_32(rs1 as i32, rs2 as i32) as usize
-    }
-
-    #[cfg(target_arch = "riscv64")]
-    unsafe {
-        _clmulh_64(rs1 as i64, rs2 as i64) as usize
-    }
-}
-
-/// Carry-less multiply (reversed)
-///
-/// clmulr produces bits 2·XLEN−2:XLEN-1 of the 2·XLEN carry-less product.
-///
-/// Source: RISC-V Bit-Manipulation ISA-extensions
-///
-/// Version: v1.0.0
-///
-/// Section: 2.13
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
-#[target_feature(enable = "zbc")]
-#[cfg_attr(test, assert_instr(clmulr))]
-#[inline]
-pub fn clmulr(rs1: usize, rs2: usize) -> usize {
-    #[cfg(target_arch = "riscv32")]
-    unsafe {
-        _clmulr_32(rs1 as i32, rs2 as i32) as usize
-    }
-
-    #[cfg(target_arch = "riscv64")]
-    unsafe {
-        _clmulr_64(rs1 as i64, rs2 as i64) as usize
-    }
-}
diff --git a/crates/core_arch/src/riscv_shared/zk.rs b/crates/core_arch/src/riscv_shared/zk.rs
index 589ea97798..0fcf13c7ac 100644
--- a/crates/core_arch/src/riscv_shared/zk.rs
+++ b/crates/core_arch/src/riscv_shared/zk.rs
@@ -27,80 +27,6 @@ unsafe extern "llvm-intrinsic" {
     fn _sha256sum1(rs1: i32) -> i32;
 }
 
-#[cfg(target_arch = "riscv32")]
-unsafe extern "llvm-intrinsic" {
-    #[link_name = "llvm.riscv.xperm8.i32"]
-    fn _xperm8_32(rs1: i32, rs2: i32) -> i32;
-
-    #[link_name = "llvm.riscv.xperm4.i32"]
-    fn _xperm4_32(rs1: i32, rs2: i32) -> i32;
-}
-
-#[cfg(target_arch = "riscv64")]
-unsafe extern "llvm-intrinsic" {
-    #[link_name = "llvm.riscv.xperm8.i64"]
-    fn _xperm8_64(rs1: i64, rs2: i64) -> i64;
-
-    #[link_name = "llvm.riscv.xperm4.i64"]
-    fn _xperm4_64(rs1: i64, rs2: i64) -> i64;
-}
-
-/// Byte-wise lookup of indicies into a vector in registers.
-///
-/// The xperm8 instruction operates on bytes. The rs1 register contains a vector of XLEN/8
-/// 8-bit elements. The rs2 register contains a vector of XLEN/8 8-bit indexes. The result is
-/// each element in rs2 replaced by the indexed element in rs1, or zero if the index into rs2
-/// is out of bounds.
-///
-/// Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions
-///
-/// Version: v1.0.1
-///
-/// Section: 3.47
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
-#[target_feature(enable = "zbkx")]
-#[cfg_attr(test, assert_instr(xperm8))]
-#[inline]
-pub fn xperm8(rs1: usize, rs2: usize) -> usize {
-    #[cfg(target_arch = "riscv32")]
-    unsafe {
-        _xperm8_32(rs1 as i32, rs2 as i32) as usize
-    }
-
-    #[cfg(target_arch = "riscv64")]
-    unsafe {
-        _xperm8_64(rs1 as i64, rs2 as i64) as usize
-    }
-}
-
-/// Nibble-wise lookup of indicies into a vector.
-///
-/// The xperm4 instruction operates on nibbles. The rs1 register contains a vector of XLEN/4
-/// 4-bit elements. The rs2 register contains a vector of XLEN/4 4-bit indexes. The result is
-/// each element in rs2 replaced by the indexed element in rs1, or zero if the index into rs2
-/// is out of bounds.
-///
-/// Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions
-///
-/// Version: v1.0.1
-///
-/// Section: 3.48
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
-#[target_feature(enable = "zbkx")]
-#[cfg_attr(test, assert_instr(xperm4))]
-#[inline]
-pub fn xperm4(rs1: usize, rs2: usize) -> usize {
-    #[cfg(target_arch = "riscv32")]
-    unsafe {
-        _xperm4_32(rs1 as i32, rs2 as i32) as usize
-    }
-
-    #[cfg(target_arch = "riscv64")]
-    unsafe {
-        _xperm4_64(rs1 as i64, rs2 as i64) as usize
-    }
-}
-
 /// Implements the Sigma0 transformation function as used in the SHA2-256 hash function \[49\]
 /// (Section 4.1.2).
 ///

From 384fd124f17ad49249b634bc9c95776413a39054 Mon Sep 17 00:00:00 2001
From: TechnoPorg <mail@technop.org>
Date: Mon, 12 Oct 2026 10:16:39 -0400
Subject: [PATCH 2/6] refactor: move zip, unzip into zb.rs

---
 crates/core_arch/src/riscv32/zb.rs | 47 ++++++++++++++++++++++++++++++
 crates/core_arch/src/riscv32/zk.rs | 47 ------------------------------
 2 files changed, 47 insertions(+), 47 deletions(-)

diff --git a/crates/core_arch/src/riscv32/zb.rs b/crates/core_arch/src/riscv32/zb.rs
index ccde8134b8..828acbd96d 100644
--- a/crates/core_arch/src/riscv32/zb.rs
+++ b/crates/core_arch/src/riscv32/zb.rs
@@ -19,6 +19,12 @@ unsafe extern "llvm-intrinsic" {
 
     #[link_name = "llvm.riscv.clmulr.i32"]
     fn _clmulr(rs1: i32, rs2: i32) -> i32;
+
+    #[link_name = "llvm.riscv.zip.i32"]
+    fn _zip(rs1: i32) -> i32;
+
+    #[link_name = "llvm.riscv.unzip.i32"]
+    fn _unzip(rs1: i32) -> i32;
 }
 
 /// Byte-wise lookup of indices into a vector in registers.
@@ -130,3 +136,44 @@ pub fn clmulh(rs1: u32, rs2: u32) -> u32 {
 pub fn clmulr(rs1: u32, rs2: u32) -> u32 {
     unsafe { _clmulr(rs1 as i32, rs2 as i32) as u32 }
 }
+
+/// Place upper/lower halves of the source register into odd/even bits of the destination
+/// respectivley.
+///
+/// This instruction places bits in the low half of the source register into the even bit
+/// positions of the destination, and bits in the high half of the source register into the odd
+/// bit positions of the destination. It is the inverse of the unzip instruction. This
+/// instruction is available only on RV32.
+///
+/// Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions
+///
+/// Version: v1.0.1
+///
+/// Section: 3.49
+#[target_feature(enable = "zbkb")]
+// See #1464
+// #[cfg_attr(test, assert_instr(zip))]
+#[inline]
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+pub fn zip(rs: u32) -> u32 {
+    unsafe { _zip(rs as i32) as u32 }
+}
+
+/// Place odd and even bits of the source word into upper/lower halves of the destination.
+///
+/// This instruction places the even bits of the source register into the low half of the
+/// destination, and the odd bits of the source into the high bits of the destination. It is
+/// the inverse of the zip instruction. This instruction is available only on RV32.
+///
+/// Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions
+///
+/// Version: v1.0.1
+///
+/// Section: 3.45
+#[target_feature(enable = "zbkb")]
+#[cfg_attr(test, assert_instr(unzip))]
+#[inline]
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+pub fn unzip(rs: u32) -> u32 {
+    unsafe { _unzip(rs as i32) as u32 }
+}
diff --git a/crates/core_arch/src/riscv32/zk.rs b/crates/core_arch/src/riscv32/zk.rs
index 3ffe0819e7..1613245182 100644
--- a/crates/core_arch/src/riscv32/zk.rs
+++ b/crates/core_arch/src/riscv32/zk.rs
@@ -14,12 +14,6 @@ unsafe extern "llvm-intrinsic" {
     #[link_name = "llvm.riscv.aes32dsmi"]
     fn _aes32dsmi(rs1: i32, rs2: i32, bs: i32) -> i32;
 
-    #[link_name = "llvm.riscv.zip.i32"]
-    fn _zip(rs1: i32) -> i32;
-
-    #[link_name = "llvm.riscv.unzip.i32"]
-    fn _unzip(rs1: i32) -> i32;
-
     #[link_name = "llvm.riscv.sha512sig0h"]
     fn _sha512sig0h(rs1: i32, rs2: i32) -> i32;
 
@@ -154,47 +148,6 @@ pub fn aes32dsmi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
     unsafe { _aes32dsmi(rs1 as i32, rs2 as i32, BS as i32) as u32 }
 }
 
-/// Place upper/lower halves of the source register into odd/even bits of the destination
-/// respectivley.
-///
-/// This instruction places bits in the low half of the source register into the even bit
-/// positions of the destination, and bits in the high half of the source register into the odd
-/// bit positions of the destination. It is the inverse of the unzip instruction. This
-/// instruction is available only on RV32.
-///
-/// Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions
-///
-/// Version: v1.0.1
-///
-/// Section: 3.49
-#[target_feature(enable = "zbkb")]
-// See #1464
-// #[cfg_attr(test, assert_instr(zip))]
-#[inline]
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
-pub fn zip(rs: u32) -> u32 {
-    unsafe { _zip(rs as i32) as u32 }
-}
-
-/// Place odd and even bits of the source word into upper/lower halves of the destination.
-///
-/// This instruction places the even bits of the source register into the low half of the
-/// destination, and the odd bits of the source into the high bits of the destination. It is
-/// the inverse of the zip instruction. This instruction is available only on RV32.
-///
-/// Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions
-///
-/// Version: v1.0.1
-///
-/// Section: 3.45
-#[target_feature(enable = "zbkb")]
-#[cfg_attr(test, assert_instr(unzip))]
-#[inline]
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
-pub fn unzip(rs: u32) -> u32 {
-    unsafe { _unzip(rs as i32) as u32 }
-}
-
 /// Implements the high half of the Sigma0 transformation, as used in the SHA2-512 hash
 /// function \[49\] (Section 4.1.3).
 ///

From 58650b6366a9acf909f06cc642b52559980a2825 Mon Sep 17 00:00:00 2001
From: TechnoPorg <mail@technop.org>
Date: Fri, 9 Oct 2026 09:04:57 -0400
Subject: [PATCH 3/6] Stabilize RISC-V `Zk` and `Zb` intrinsics

---
 crates/core_arch/src/riscv32/mod.rs      |  4 ++--
 crates/core_arch/src/riscv32/zb.rs       | 16 ++++++++--------
 crates/core_arch/src/riscv32/zk.rs       | 20 ++++++++++----------
 crates/core_arch/src/riscv64/mod.rs      |  4 ++--
 crates/core_arch/src/riscv64/zb.rs       | 12 ++++++------
 crates/core_arch/src/riscv64/zk.rs       | 22 +++++++++++-----------
 crates/core_arch/src/riscv_shared/mod.rs |  2 +-
 crates/core_arch/src/riscv_shared/zk.rs  | 16 ++++++++--------
 8 files changed, 48 insertions(+), 48 deletions(-)

diff --git a/crates/core_arch/src/riscv32/mod.rs b/crates/core_arch/src/riscv32/mod.rs
index 7017b7edc4..298f2bb0f0 100644
--- a/crates/core_arch/src/riscv32/mod.rs
+++ b/crates/core_arch/src/riscv32/mod.rs
@@ -3,8 +3,8 @@
 mod zb;
 mod zk;
 
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub use zb::*;
 
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub use zk::*;
diff --git a/crates/core_arch/src/riscv32/zb.rs b/crates/core_arch/src/riscv32/zb.rs
index 828acbd96d..439e6d0670 100644
--- a/crates/core_arch/src/riscv32/zb.rs
+++ b/crates/core_arch/src/riscv32/zb.rs
@@ -39,7 +39,7 @@ unsafe extern "llvm-intrinsic" {
 /// Version: v1.0.1
 ///
 /// Section: 3.47
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zbkx")]
 #[cfg_attr(test, assert_instr(xperm8))]
 #[inline]
@@ -59,7 +59,7 @@ pub fn xperm8(rs1: u32, rs2: u32) -> u32 {
 /// Version: v1.0.1
 ///
 /// Section: 3.48
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zbkx")]
 #[cfg_attr(test, assert_instr(xperm4))]
 #[inline]
@@ -78,7 +78,7 @@ pub fn xperm4(rs1: u32, rs2: u32) -> u32 {
 /// Version: v1.0.0
 ///
 /// Section: 2.24
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zbb")]
 #[cfg_attr(test, assert_instr(orc.b))]
 #[inline]
@@ -95,7 +95,7 @@ pub fn orc_b(rs: u32) -> u32 {
 /// Version: v1.0.0
 ///
 /// Section: 2.11
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zbkc")]
 #[cfg_attr(test, assert_instr(clmul))]
 #[inline]
@@ -112,7 +112,7 @@ pub fn clmul(rs1: u32, rs2: u32) -> u32 {
 /// Version: v1.0.0
 ///
 /// Section: 2.12
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zbkc")]
 #[cfg_attr(test, assert_instr(clmulh))]
 #[inline]
@@ -129,7 +129,7 @@ pub fn clmulh(rs1: u32, rs2: u32) -> u32 {
 /// Version: v1.0.0
 ///
 /// Section: 2.13
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zbc")]
 #[cfg_attr(test, assert_instr(clmulr))]
 #[inline]
@@ -154,7 +154,7 @@ pub fn clmulr(rs1: u32, rs2: u32) -> u32 {
 // See #1464
 // #[cfg_attr(test, assert_instr(zip))]
 #[inline]
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn zip(rs: u32) -> u32 {
     unsafe { _zip(rs as i32) as u32 }
 }
@@ -173,7 +173,7 @@ pub fn zip(rs: u32) -> u32 {
 #[target_feature(enable = "zbkb")]
 #[cfg_attr(test, assert_instr(unzip))]
 #[inline]
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zb_intrinsics", issue = "CURRENT_RUSTC_VERSION")]
 pub fn unzip(rs: u32) -> u32 {
     unsafe { _unzip(rs as i32) as u32 }
 }
diff --git a/crates/core_arch/src/riscv32/zk.rs b/crates/core_arch/src/riscv32/zk.rs
index 1613245182..c873b0371a 100644
--- a/crates/core_arch/src/riscv32/zk.rs
+++ b/crates/core_arch/src/riscv32/zk.rs
@@ -55,7 +55,7 @@ unsafe extern "llvm-intrinsic" {
 // See #1464
 // #[cfg_attr(test, assert_instr(aes32esi, BS = 0))]
 #[inline]
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn aes32esi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
     static_assert!(BS < 4);
 
@@ -84,7 +84,7 @@ pub fn aes32esi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
 // See #1464
 // #[cfg_attr(test, assert_instr(aes32esmi, BS = 0))]
 #[inline]
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn aes32esmi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
     static_assert!(BS < 4);
 
@@ -112,7 +112,7 @@ pub fn aes32esmi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
 // See #1464
 // #[cfg_attr(test, assert_instr(aes32dsi, BS = 0))]
 #[inline]
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn aes32dsi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
     static_assert!(BS < 4);
 
@@ -141,7 +141,7 @@ pub fn aes32dsi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
 // See #1464
 // #[cfg_attr(test, assert_instr(aes32dsmi, BS = 0))]
 #[inline]
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn aes32dsmi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
     static_assert!(BS < 4);
 
@@ -166,7 +166,7 @@ pub fn aes32dsmi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
 // See #1464
 // #[cfg_attr(test, assert_instr(sha512sig0h))]
 #[inline]
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn sha512sig0h(rs1: u32, rs2: u32) -> u32 {
     unsafe { _sha512sig0h(rs1 as i32, rs2 as i32) as u32 }
 }
@@ -189,7 +189,7 @@ pub fn sha512sig0h(rs1: u32, rs2: u32) -> u32 {
 // See #1464
 // #[cfg_attr(test, assert_instr(sha512sig0l))]
 #[inline]
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn sha512sig0l(rs1: u32, rs2: u32) -> u32 {
     unsafe { _sha512sig0l(rs1 as i32, rs2 as i32) as u32 }
 }
@@ -212,7 +212,7 @@ pub fn sha512sig0l(rs1: u32, rs2: u32) -> u32 {
 // See #1464
 // #[cfg_attr(test, assert_instr(sha512sig1h))]
 #[inline]
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn sha512sig1h(rs1: u32, rs2: u32) -> u32 {
     unsafe { _sha512sig1h(rs1 as i32, rs2 as i32) as u32 }
 }
@@ -234,7 +234,7 @@ pub fn sha512sig1h(rs1: u32, rs2: u32) -> u32 {
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha512sig1l))]
 #[inline]
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn sha512sig1l(rs1: u32, rs2: u32) -> u32 {
     unsafe { _sha512sig1l(rs1 as i32, rs2 as i32) as u32 }
 }
@@ -256,7 +256,7 @@ pub fn sha512sig1l(rs1: u32, rs2: u32) -> u32 {
 // See #1464
 // #[cfg_attr(test, assert_instr(sha512sum0r))]
 #[inline]
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn sha512sum0r(rs1: u32, rs2: u32) -> u32 {
     unsafe { _sha512sum0r(rs1 as i32, rs2 as i32) as u32 }
 }
@@ -278,7 +278,7 @@ pub fn sha512sum0r(rs1: u32, rs2: u32) -> u32 {
 // See #1464
 // #[cfg_attr(test, assert_instr(sha512sum1r))]
 #[inline]
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn sha512sum1r(rs1: u32, rs2: u32) -> u32 {
     unsafe { _sha512sum1r(rs1 as i32, rs2 as i32) as u32 }
 }
diff --git a/crates/core_arch/src/riscv64/mod.rs b/crates/core_arch/src/riscv64/mod.rs
index 8301ea2b23..c158621b79 100644
--- a/crates/core_arch/src/riscv64/mod.rs
+++ b/crates/core_arch/src/riscv64/mod.rs
@@ -4,10 +4,10 @@ use crate::arch::asm;
 mod zb;
 mod zk;
 
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub use zb::*;
 
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub use zk::*;
 
 /// Loads virtual machine memory by unsigned word integer
diff --git a/crates/core_arch/src/riscv64/zb.rs b/crates/core_arch/src/riscv64/zb.rs
index 9e1ac328bc..b7f873e0d7 100644
--- a/crates/core_arch/src/riscv64/zb.rs
+++ b/crates/core_arch/src/riscv64/zb.rs
@@ -33,7 +33,7 @@ unsafe extern "llvm-intrinsic" {
 /// Version: v1.0.1
 ///
 /// Section: 3.47
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zbkx")]
 #[cfg_attr(test, assert_instr(xperm8))]
 #[inline]
@@ -53,7 +53,7 @@ pub fn xperm8(rs1: u64, rs2: u64) -> u64 {
 /// Version: v1.0.1
 ///
 /// Section: 3.48
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zbkx")]
 #[cfg_attr(test, assert_instr(xperm4))]
 #[inline]
@@ -72,7 +72,7 @@ pub fn xperm4(rs1: u64, rs2: u64) -> u64 {
 /// Version: v1.0.0
 ///
 /// Section: 2.24
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zbb")]
 #[cfg_attr(test, assert_instr(orc.b))]
 #[inline]
@@ -89,7 +89,7 @@ pub fn orc_b(rs: u64) -> u64 {
 /// Version: v1.0.0
 ///
 /// Section: 2.11
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zbkc")]
 #[cfg_attr(test, assert_instr(clmul))]
 #[inline]
@@ -106,7 +106,7 @@ pub fn clmul(rs1: u64, rs2: u64) -> u64 {
 /// Version: v1.0.0
 ///
 /// Section: 2.12
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zbkc")]
 #[cfg_attr(test, assert_instr(clmulh))]
 #[inline]
@@ -123,7 +123,7 @@ pub fn clmulh(rs1: u64, rs2: u64) -> u64 {
 /// Version: v1.0.0
 ///
 /// Section: 2.13
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zbc")]
 #[cfg_attr(test, assert_instr(clmulr))]
 #[inline]
diff --git a/crates/core_arch/src/riscv64/zk.rs b/crates/core_arch/src/riscv64/zk.rs
index 21cfefafdd..fdc3ee8e2b 100644
--- a/crates/core_arch/src/riscv64/zk.rs
+++ b/crates/core_arch/src/riscv64/zk.rs
@@ -47,7 +47,7 @@ unsafe extern "llvm-intrinsic" {
 #[target_feature(enable = "zkne")]
 #[cfg_attr(test, assert_instr(aes64es))]
 #[inline]
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn aes64es(rs1: u64, rs2: u64) -> u64 {
     unsafe { _aes64es(rs1 as i64, rs2 as i64) as u64 }
 }
@@ -67,7 +67,7 @@ pub fn aes64es(rs1: u64, rs2: u64) -> u64 {
 #[target_feature(enable = "zkne")]
 #[cfg_attr(test, assert_instr(aes64esm))]
 #[inline]
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn aes64esm(rs1: u64, rs2: u64) -> u64 {
     unsafe { _aes64esm(rs1 as i64, rs2 as i64) as u64 }
 }
@@ -87,7 +87,7 @@ pub fn aes64esm(rs1: u64, rs2: u64) -> u64 {
 #[target_feature(enable = "zknd")]
 #[cfg_attr(test, assert_instr(aes64ds))]
 #[inline]
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn aes64ds(rs1: u64, rs2: u64) -> u64 {
     unsafe { _aes64ds(rs1 as i64, rs2 as i64) as u64 }
 }
@@ -107,7 +107,7 @@ pub fn aes64ds(rs1: u64, rs2: u64) -> u64 {
 #[target_feature(enable = "zknd")]
 #[cfg_attr(test, assert_instr(aes64dsm))]
 #[inline]
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn aes64dsm(rs1: u64, rs2: u64) -> u64 {
     unsafe { _aes64dsm(rs1 as i64, rs2 as i64) as u64 }
 }
@@ -132,7 +132,7 @@ pub fn aes64dsm(rs1: u64, rs2: u64) -> u64 {
 #[target_feature(enable = "zkne_or_zknd")]
 #[rustc_legacy_const_generics(1)]
 #[inline]
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn aes64ks1i<const RNUM: u8>(rs1: u64) -> u64 {
     static_assert!(RNUM <= 10);
     unsafe {
@@ -164,7 +164,7 @@ pub fn aes64ks1i<const RNUM: u8>(rs1: u64) -> u64 {
 /// Section: 3.11
 #[target_feature(enable = "zkne_or_zknd")]
 #[inline]
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn aes64ks2(rs1: u64, rs2: u64) -> u64 {
     unsafe {
         let rd: u64;
@@ -198,7 +198,7 @@ pub fn aes64ks2(rs1: u64, rs2: u64) -> u64 {
 #[target_feature(enable = "zknd")]
 #[cfg_attr(test, assert_instr(aes64im))]
 #[inline]
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn aes64im(rs1: u64) -> u64 {
     unsafe { _aes64im(rs1 as i64) as u64 }
 }
@@ -218,7 +218,7 @@ pub fn aes64im(rs1: u64) -> u64 {
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha512sig0))]
 #[inline]
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn sha512sig0(rs1: u64) -> u64 {
     unsafe { _sha512sig0(rs1 as i64) as u64 }
 }
@@ -238,7 +238,7 @@ pub fn sha512sig0(rs1: u64) -> u64 {
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha512sig1))]
 #[inline]
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn sha512sig1(rs1: u64) -> u64 {
     unsafe { _sha512sig1(rs1 as i64) as u64 }
 }
@@ -258,7 +258,7 @@ pub fn sha512sig1(rs1: u64) -> u64 {
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha512sum0))]
 #[inline]
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn sha512sum0(rs1: u64) -> u64 {
     unsafe { _sha512sum0(rs1 as i64) as u64 }
 }
@@ -278,7 +278,7 @@ pub fn sha512sum0(rs1: u64) -> u64 {
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha512sum1))]
 #[inline]
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn sha512sum1(rs1: u64) -> u64 {
     unsafe { _sha512sum1(rs1 as i64) as u64 }
 }
diff --git a/crates/core_arch/src/riscv_shared/mod.rs b/crates/core_arch/src/riscv_shared/mod.rs
index bb6549f8e1..21eb0c7756 100644
--- a/crates/core_arch/src/riscv_shared/mod.rs
+++ b/crates/core_arch/src/riscv_shared/mod.rs
@@ -29,7 +29,7 @@ mod zk;
 
 #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub use p::*;
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub use zk::*;
 
 use crate::arch::asm;
diff --git a/crates/core_arch/src/riscv_shared/zk.rs b/crates/core_arch/src/riscv_shared/zk.rs
index 0fcf13c7ac..f97845366f 100644
--- a/crates/core_arch/src/riscv_shared/zk.rs
+++ b/crates/core_arch/src/riscv_shared/zk.rs
@@ -42,7 +42,7 @@ unsafe extern "llvm-intrinsic" {
 /// Version: v1.0.1
 ///
 /// Section: 3.27
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha256sig0))]
 #[inline]
@@ -65,7 +65,7 @@ pub fn sha256sig0(rs1: u32) -> u32 {
 /// Version: v1.0.1
 ///
 /// Section: 3.28
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha256sig1))]
 #[inline]
@@ -88,7 +88,7 @@ pub fn sha256sig1(rs1: u32) -> u32 {
 /// Version: v1.0.1
 ///
 /// Section: 3.29
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha256sum0))]
 #[inline]
@@ -111,7 +111,7 @@ pub fn sha256sum0(rs1: u32) -> u32 {
 /// Version: v1.0.1
 ///
 /// Section: 3.30
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha256sum1))]
 #[inline]
@@ -184,7 +184,7 @@ pub fn sha256sum1(rs1: u32) -> u32 {
 /// return c3; // c3 represents c[0..=3]
 /// # }
 /// ```
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zksed")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(sm4ed, BS = 0))]
@@ -260,7 +260,7 @@ pub fn sm4ed<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
 /// return c3; // c3 represents c[0..=3]
 /// # }
 /// ```
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zksed")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(sm4ks, BS = 0))]
@@ -298,7 +298,7 @@ pub fn sm4ks<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
 /// In the SM3 algorithm, the `P0` transformation is used as `E ← P0(TT2)` when the
 /// compression function `CF` uses the intermediate value `TT2` to calculate
 /// the variable `E` in one iteration for subsequent processes.
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zksh")]
 #[cfg_attr(test, assert_instr(sm3p0))]
 #[inline]
@@ -339,7 +339,7 @@ pub fn sm3p0(rs1: u32) -> u32 {
 ///     Wj ← P1(Wj−16 ⊕ Wj−9 ⊕ (Wj−3 ≪ 15)) ⊕ (Wj−13 ≪ 7) ⊕ Wj−6
 /// ENDFOR
 /// ```
-#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zksh")]
 #[cfg_attr(test, assert_instr(sm3p1))]
 #[inline]

From 96ef0e8f115f780f4b4475688705b03201e37b21 Mon Sep 17 00:00:00 2001
From: TechnoPorg <mail@technop.org>
Date: Mon, 12 Oct 2026 10:37:38 -0400
Subject: [PATCH 4/6] fix: uncomment assert_instr tests

I'm not sure when this started working, but I didn't have the problem in issue 1464.
---
 crates/core_arch/src/riscv32/zb.rs |  5 ++---
 crates/core_arch/src/riscv32/zk.rs | 27 +++++++++------------------
 2 files changed, 11 insertions(+), 21 deletions(-)

diff --git a/crates/core_arch/src/riscv32/zb.rs b/crates/core_arch/src/riscv32/zb.rs
index 439e6d0670..58daf17346 100644
--- a/crates/core_arch/src/riscv32/zb.rs
+++ b/crates/core_arch/src/riscv32/zb.rs
@@ -151,8 +151,7 @@ pub fn clmulr(rs1: u32, rs2: u32) -> u32 {
 ///
 /// Section: 3.49
 #[target_feature(enable = "zbkb")]
-// See #1464
-// #[cfg_attr(test, assert_instr(zip))]
+#[cfg_attr(test, assert_instr(zip))]
 #[inline]
 #[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn zip(rs: u32) -> u32 {
@@ -173,7 +172,7 @@ pub fn zip(rs: u32) -> u32 {
 #[target_feature(enable = "zbkb")]
 #[cfg_attr(test, assert_instr(unzip))]
 #[inline]
-#[stable(feature = "riscv_zb_intrinsics", issue = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn unzip(rs: u32) -> u32 {
     unsafe { _unzip(rs as i32) as u32 }
 }
diff --git a/crates/core_arch/src/riscv32/zk.rs b/crates/core_arch/src/riscv32/zk.rs
index c873b0371a..e4a6371178 100644
--- a/crates/core_arch/src/riscv32/zk.rs
+++ b/crates/core_arch/src/riscv32/zk.rs
@@ -52,8 +52,7 @@ unsafe extern "llvm-intrinsic" {
 /// used.
 #[target_feature(enable = "zkne")]
 #[rustc_legacy_const_generics(2)]
-// See #1464
-// #[cfg_attr(test, assert_instr(aes32esi, BS = 0))]
+#[cfg_attr(test, assert_instr(aes32esi, BS = 0))]
 #[inline]
 #[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn aes32esi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
@@ -81,8 +80,7 @@ pub fn aes32esi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
 /// used.
 #[target_feature(enable = "zkne")]
 #[rustc_legacy_const_generics(2)]
-// See #1464
-// #[cfg_attr(test, assert_instr(aes32esmi, BS = 0))]
+#[cfg_attr(test, assert_instr(aes32esmi, BS = 0))]
 #[inline]
 #[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn aes32esmi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
@@ -109,8 +107,7 @@ pub fn aes32esmi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
 /// used.
 #[target_feature(enable = "zknd")]
 #[rustc_legacy_const_generics(2)]
-// See #1464
-// #[cfg_attr(test, assert_instr(aes32dsi, BS = 0))]
+#[cfg_attr(test, assert_instr(aes32dsi, BS = 0))]
 #[inline]
 #[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn aes32dsi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
@@ -138,8 +135,7 @@ pub fn aes32dsi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
 /// used.
 #[target_feature(enable = "zknd")]
 #[rustc_legacy_const_generics(2)]
-// See #1464
-// #[cfg_attr(test, assert_instr(aes32dsmi, BS = 0))]
+#[cfg_attr(test, assert_instr(aes32dsmi, BS = 0))]
 #[inline]
 #[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn aes32dsmi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
@@ -163,8 +159,7 @@ pub fn aes32dsmi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
 ///
 /// Section: 3.31
 #[target_feature(enable = "zknh")]
-// See #1464
-// #[cfg_attr(test, assert_instr(sha512sig0h))]
+#[cfg_attr(test, assert_instr(sha512sig0h))]
 #[inline]
 #[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn sha512sig0h(rs1: u32, rs2: u32) -> u32 {
@@ -186,8 +181,7 @@ pub fn sha512sig0h(rs1: u32, rs2: u32) -> u32 {
 ///
 /// Section: 3.32
 #[target_feature(enable = "zknh")]
-// See #1464
-// #[cfg_attr(test, assert_instr(sha512sig0l))]
+#[cfg_attr(test, assert_instr(sha512sig0l))]
 #[inline]
 #[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn sha512sig0l(rs1: u32, rs2: u32) -> u32 {
@@ -209,8 +203,7 @@ pub fn sha512sig0l(rs1: u32, rs2: u32) -> u32 {
 ///
 /// Section: 3.33
 #[target_feature(enable = "zknh")]
-// See #1464
-// #[cfg_attr(test, assert_instr(sha512sig1h))]
+#[cfg_attr(test, assert_instr(sha512sig1h))]
 #[inline]
 #[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn sha512sig1h(rs1: u32, rs2: u32) -> u32 {
@@ -253,8 +246,7 @@ pub fn sha512sig1l(rs1: u32, rs2: u32) -> u32 {
 ///
 /// Section: 3.35
 #[target_feature(enable = "zknh")]
-// See #1464
-// #[cfg_attr(test, assert_instr(sha512sum0r))]
+#[cfg_attr(test, assert_instr(sha512sum0r))]
 #[inline]
 #[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn sha512sum0r(rs1: u32, rs2: u32) -> u32 {
@@ -275,8 +267,7 @@ pub fn sha512sum0r(rs1: u32, rs2: u32) -> u32 {
 ///
 /// Section: 3.36
 #[target_feature(enable = "zknh")]
-// See #1464
-// #[cfg_attr(test, assert_instr(sha512sum1r))]
+#[cfg_attr(test, assert_instr(sha512sum1r))]
 #[inline]
 #[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
 pub fn sha512sum1r(rs1: u32, rs2: u32) -> u32 {

From fbc461bfd83d2249441cb1445b70b813552a795d Mon Sep 17 00:00:00 2001
From: TechnoPorg <mail@technop.org>
Date: Mon, 12 Oct 2026 10:48:08 -0400
Subject: [PATCH 5/6] fix: feature names, module stability

---
 crates/core_arch/src/mod.rs              |  4 ++--
 crates/core_arch/src/riscv32/mod.rs      |  4 ++--
 crates/core_arch/src/riscv32/zb.rs       | 16 ++++++++--------
 crates/core_arch/src/riscv32/zk.rs       | 20 ++++++++++----------
 crates/core_arch/src/riscv64/mod.rs      |  4 ++--
 crates/core_arch/src/riscv64/zb.rs       | 12 ++++++------
 crates/core_arch/src/riscv64/zk.rs       | 22 +++++++++++-----------
 crates/core_arch/src/riscv_shared/mod.rs |  2 +-
 crates/core_arch/src/riscv_shared/zk.rs  | 16 ++++++++--------
 9 files changed, 50 insertions(+), 50 deletions(-)

diff --git a/crates/core_arch/src/mod.rs b/crates/core_arch/src/mod.rs
index ab787590a2..edad99ecbb 100644
--- a/crates/core_arch/src/mod.rs
+++ b/crates/core_arch/src/mod.rs
@@ -83,7 +83,7 @@ pub mod arch {
     /// See the [module documentation](../index.html) for more details.
     #[cfg(any(target_arch = "riscv32", doc))]
     #[doc(cfg(any(target_arch = "riscv32")))]
-    #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+    #[stable(feature = "stdarch_riscv", since = "CURRENT_RUSTC_VERSION")]
     pub mod riscv32 {
         pub use crate::core_arch::riscv_shared::*;
         pub use crate::core_arch::riscv32::*;
@@ -94,7 +94,7 @@ pub mod arch {
     /// See the [module documentation](../index.html) for more details.
     #[cfg(any(target_arch = "riscv64", doc))]
     #[doc(cfg(any(target_arch = "riscv64")))]
-    #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
+    #[stable(feature = "stdarch_riscv", since = "CURRENT_RUSTC_VERSION")]
     pub mod riscv64 {
         pub use crate::core_arch::riscv64::*;
         // RISC-V RV64 supports all RV32 instructions as well in current specifications (2022-01-05).
diff --git a/crates/core_arch/src/riscv32/mod.rs b/crates/core_arch/src/riscv32/mod.rs
index 298f2bb0f0..fbcbc02783 100644
--- a/crates/core_arch/src/riscv32/mod.rs
+++ b/crates/core_arch/src/riscv32/mod.rs
@@ -3,8 +3,8 @@
 mod zb;
 mod zk;
 
-#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zb", since = "CURRENT_RUSTC_VERSION")]
 pub use zb::*;
 
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 pub use zk::*;
diff --git a/crates/core_arch/src/riscv32/zb.rs b/crates/core_arch/src/riscv32/zb.rs
index 58daf17346..f8b92ec9fb 100644
--- a/crates/core_arch/src/riscv32/zb.rs
+++ b/crates/core_arch/src/riscv32/zb.rs
@@ -39,7 +39,7 @@ unsafe extern "llvm-intrinsic" {
 /// Version: v1.0.1
 ///
 /// Section: 3.47
-#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zb", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zbkx")]
 #[cfg_attr(test, assert_instr(xperm8))]
 #[inline]
@@ -59,7 +59,7 @@ pub fn xperm8(rs1: u32, rs2: u32) -> u32 {
 /// Version: v1.0.1
 ///
 /// Section: 3.48
-#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zb", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zbkx")]
 #[cfg_attr(test, assert_instr(xperm4))]
 #[inline]
@@ -78,7 +78,7 @@ pub fn xperm4(rs1: u32, rs2: u32) -> u32 {
 /// Version: v1.0.0
 ///
 /// Section: 2.24
-#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zb", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zbb")]
 #[cfg_attr(test, assert_instr(orc.b))]
 #[inline]
@@ -95,7 +95,7 @@ pub fn orc_b(rs: u32) -> u32 {
 /// Version: v1.0.0
 ///
 /// Section: 2.11
-#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zb", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zbkc")]
 #[cfg_attr(test, assert_instr(clmul))]
 #[inline]
@@ -112,7 +112,7 @@ pub fn clmul(rs1: u32, rs2: u32) -> u32 {
 /// Version: v1.0.0
 ///
 /// Section: 2.12
-#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zb", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zbkc")]
 #[cfg_attr(test, assert_instr(clmulh))]
 #[inline]
@@ -129,7 +129,7 @@ pub fn clmulh(rs1: u32, rs2: u32) -> u32 {
 /// Version: v1.0.0
 ///
 /// Section: 2.13
-#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zb", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zbc")]
 #[cfg_attr(test, assert_instr(clmulr))]
 #[inline]
@@ -153,7 +153,7 @@ pub fn clmulr(rs1: u32, rs2: u32) -> u32 {
 #[target_feature(enable = "zbkb")]
 #[cfg_attr(test, assert_instr(zip))]
 #[inline]
-#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zb", since = "CURRENT_RUSTC_VERSION")]
 pub fn zip(rs: u32) -> u32 {
     unsafe { _zip(rs as i32) as u32 }
 }
@@ -172,7 +172,7 @@ pub fn zip(rs: u32) -> u32 {
 #[target_feature(enable = "zbkb")]
 #[cfg_attr(test, assert_instr(unzip))]
 #[inline]
-#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zb", since = "CURRENT_RUSTC_VERSION")]
 pub fn unzip(rs: u32) -> u32 {
     unsafe { _unzip(rs as i32) as u32 }
 }
diff --git a/crates/core_arch/src/riscv32/zk.rs b/crates/core_arch/src/riscv32/zk.rs
index e4a6371178..a20dad12cb 100644
--- a/crates/core_arch/src/riscv32/zk.rs
+++ b/crates/core_arch/src/riscv32/zk.rs
@@ -54,7 +54,7 @@ unsafe extern "llvm-intrinsic" {
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(aes32esi, BS = 0))]
 #[inline]
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 pub fn aes32esi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
     static_assert!(BS < 4);
 
@@ -82,7 +82,7 @@ pub fn aes32esi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(aes32esmi, BS = 0))]
 #[inline]
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 pub fn aes32esmi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
     static_assert!(BS < 4);
 
@@ -109,7 +109,7 @@ pub fn aes32esmi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(aes32dsi, BS = 0))]
 #[inline]
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 pub fn aes32dsi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
     static_assert!(BS < 4);
 
@@ -137,7 +137,7 @@ pub fn aes32dsi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(aes32dsmi, BS = 0))]
 #[inline]
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 pub fn aes32dsmi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
     static_assert!(BS < 4);
 
@@ -161,7 +161,7 @@ pub fn aes32dsmi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha512sig0h))]
 #[inline]
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 pub fn sha512sig0h(rs1: u32, rs2: u32) -> u32 {
     unsafe { _sha512sig0h(rs1 as i32, rs2 as i32) as u32 }
 }
@@ -183,7 +183,7 @@ pub fn sha512sig0h(rs1: u32, rs2: u32) -> u32 {
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha512sig0l))]
 #[inline]
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 pub fn sha512sig0l(rs1: u32, rs2: u32) -> u32 {
     unsafe { _sha512sig0l(rs1 as i32, rs2 as i32) as u32 }
 }
@@ -205,7 +205,7 @@ pub fn sha512sig0l(rs1: u32, rs2: u32) -> u32 {
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha512sig1h))]
 #[inline]
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 pub fn sha512sig1h(rs1: u32, rs2: u32) -> u32 {
     unsafe { _sha512sig1h(rs1 as i32, rs2 as i32) as u32 }
 }
@@ -227,7 +227,7 @@ pub fn sha512sig1h(rs1: u32, rs2: u32) -> u32 {
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha512sig1l))]
 #[inline]
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 pub fn sha512sig1l(rs1: u32, rs2: u32) -> u32 {
     unsafe { _sha512sig1l(rs1 as i32, rs2 as i32) as u32 }
 }
@@ -248,7 +248,7 @@ pub fn sha512sig1l(rs1: u32, rs2: u32) -> u32 {
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha512sum0r))]
 #[inline]
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 pub fn sha512sum0r(rs1: u32, rs2: u32) -> u32 {
     unsafe { _sha512sum0r(rs1 as i32, rs2 as i32) as u32 }
 }
@@ -269,7 +269,7 @@ pub fn sha512sum0r(rs1: u32, rs2: u32) -> u32 {
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha512sum1r))]
 #[inline]
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 pub fn sha512sum1r(rs1: u32, rs2: u32) -> u32 {
     unsafe { _sha512sum1r(rs1 as i32, rs2 as i32) as u32 }
 }
diff --git a/crates/core_arch/src/riscv64/mod.rs b/crates/core_arch/src/riscv64/mod.rs
index c158621b79..d5b765b7fe 100644
--- a/crates/core_arch/src/riscv64/mod.rs
+++ b/crates/core_arch/src/riscv64/mod.rs
@@ -4,10 +4,10 @@ use crate::arch::asm;
 mod zb;
 mod zk;
 
-#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zb", since = "CURRENT_RUSTC_VERSION")]
 pub use zb::*;
 
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 pub use zk::*;
 
 /// Loads virtual machine memory by unsigned word integer
diff --git a/crates/core_arch/src/riscv64/zb.rs b/crates/core_arch/src/riscv64/zb.rs
index b7f873e0d7..9f21a0214a 100644
--- a/crates/core_arch/src/riscv64/zb.rs
+++ b/crates/core_arch/src/riscv64/zb.rs
@@ -33,7 +33,7 @@ unsafe extern "llvm-intrinsic" {
 /// Version: v1.0.1
 ///
 /// Section: 3.47
-#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zb", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zbkx")]
 #[cfg_attr(test, assert_instr(xperm8))]
 #[inline]
@@ -53,7 +53,7 @@ pub fn xperm8(rs1: u64, rs2: u64) -> u64 {
 /// Version: v1.0.1
 ///
 /// Section: 3.48
-#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zb", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zbkx")]
 #[cfg_attr(test, assert_instr(xperm4))]
 #[inline]
@@ -72,7 +72,7 @@ pub fn xperm4(rs1: u64, rs2: u64) -> u64 {
 /// Version: v1.0.0
 ///
 /// Section: 2.24
-#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zb", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zbb")]
 #[cfg_attr(test, assert_instr(orc.b))]
 #[inline]
@@ -89,7 +89,7 @@ pub fn orc_b(rs: u64) -> u64 {
 /// Version: v1.0.0
 ///
 /// Section: 2.11
-#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zb", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zbkc")]
 #[cfg_attr(test, assert_instr(clmul))]
 #[inline]
@@ -106,7 +106,7 @@ pub fn clmul(rs1: u64, rs2: u64) -> u64 {
 /// Version: v1.0.0
 ///
 /// Section: 2.12
-#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zb", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zbkc")]
 #[cfg_attr(test, assert_instr(clmulh))]
 #[inline]
@@ -123,7 +123,7 @@ pub fn clmulh(rs1: u64, rs2: u64) -> u64 {
 /// Version: v1.0.0
 ///
 /// Section: 2.13
-#[stable(feature = "riscv_zb_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zb", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zbc")]
 #[cfg_attr(test, assert_instr(clmulr))]
 #[inline]
diff --git a/crates/core_arch/src/riscv64/zk.rs b/crates/core_arch/src/riscv64/zk.rs
index fdc3ee8e2b..d70171a5b6 100644
--- a/crates/core_arch/src/riscv64/zk.rs
+++ b/crates/core_arch/src/riscv64/zk.rs
@@ -47,7 +47,7 @@ unsafe extern "llvm-intrinsic" {
 #[target_feature(enable = "zkne")]
 #[cfg_attr(test, assert_instr(aes64es))]
 #[inline]
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 pub fn aes64es(rs1: u64, rs2: u64) -> u64 {
     unsafe { _aes64es(rs1 as i64, rs2 as i64) as u64 }
 }
@@ -67,7 +67,7 @@ pub fn aes64es(rs1: u64, rs2: u64) -> u64 {
 #[target_feature(enable = "zkne")]
 #[cfg_attr(test, assert_instr(aes64esm))]
 #[inline]
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 pub fn aes64esm(rs1: u64, rs2: u64) -> u64 {
     unsafe { _aes64esm(rs1 as i64, rs2 as i64) as u64 }
 }
@@ -87,7 +87,7 @@ pub fn aes64esm(rs1: u64, rs2: u64) -> u64 {
 #[target_feature(enable = "zknd")]
 #[cfg_attr(test, assert_instr(aes64ds))]
 #[inline]
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 pub fn aes64ds(rs1: u64, rs2: u64) -> u64 {
     unsafe { _aes64ds(rs1 as i64, rs2 as i64) as u64 }
 }
@@ -107,7 +107,7 @@ pub fn aes64ds(rs1: u64, rs2: u64) -> u64 {
 #[target_feature(enable = "zknd")]
 #[cfg_attr(test, assert_instr(aes64dsm))]
 #[inline]
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 pub fn aes64dsm(rs1: u64, rs2: u64) -> u64 {
     unsafe { _aes64dsm(rs1 as i64, rs2 as i64) as u64 }
 }
@@ -132,7 +132,7 @@ pub fn aes64dsm(rs1: u64, rs2: u64) -> u64 {
 #[target_feature(enable = "zkne_or_zknd")]
 #[rustc_legacy_const_generics(1)]
 #[inline]
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 pub fn aes64ks1i<const RNUM: u8>(rs1: u64) -> u64 {
     static_assert!(RNUM <= 10);
     unsafe {
@@ -164,7 +164,7 @@ pub fn aes64ks1i<const RNUM: u8>(rs1: u64) -> u64 {
 /// Section: 3.11
 #[target_feature(enable = "zkne_or_zknd")]
 #[inline]
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 pub fn aes64ks2(rs1: u64, rs2: u64) -> u64 {
     unsafe {
         let rd: u64;
@@ -198,7 +198,7 @@ pub fn aes64ks2(rs1: u64, rs2: u64) -> u64 {
 #[target_feature(enable = "zknd")]
 #[cfg_attr(test, assert_instr(aes64im))]
 #[inline]
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 pub fn aes64im(rs1: u64) -> u64 {
     unsafe { _aes64im(rs1 as i64) as u64 }
 }
@@ -218,7 +218,7 @@ pub fn aes64im(rs1: u64) -> u64 {
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha512sig0))]
 #[inline]
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 pub fn sha512sig0(rs1: u64) -> u64 {
     unsafe { _sha512sig0(rs1 as i64) as u64 }
 }
@@ -238,7 +238,7 @@ pub fn sha512sig0(rs1: u64) -> u64 {
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha512sig1))]
 #[inline]
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 pub fn sha512sig1(rs1: u64) -> u64 {
     unsafe { _sha512sig1(rs1 as i64) as u64 }
 }
@@ -258,7 +258,7 @@ pub fn sha512sig1(rs1: u64) -> u64 {
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha512sum0))]
 #[inline]
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 pub fn sha512sum0(rs1: u64) -> u64 {
     unsafe { _sha512sum0(rs1 as i64) as u64 }
 }
@@ -278,7 +278,7 @@ pub fn sha512sum0(rs1: u64) -> u64 {
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha512sum1))]
 #[inline]
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 pub fn sha512sum1(rs1: u64) -> u64 {
     unsafe { _sha512sum1(rs1 as i64) as u64 }
 }
diff --git a/crates/core_arch/src/riscv_shared/mod.rs b/crates/core_arch/src/riscv_shared/mod.rs
index 21eb0c7756..bdbe02f9ab 100644
--- a/crates/core_arch/src/riscv_shared/mod.rs
+++ b/crates/core_arch/src/riscv_shared/mod.rs
@@ -29,7 +29,7 @@ mod zk;
 
 #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub use p::*;
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 pub use zk::*;
 
 use crate::arch::asm;
diff --git a/crates/core_arch/src/riscv_shared/zk.rs b/crates/core_arch/src/riscv_shared/zk.rs
index f97845366f..0bdd52ef30 100644
--- a/crates/core_arch/src/riscv_shared/zk.rs
+++ b/crates/core_arch/src/riscv_shared/zk.rs
@@ -42,7 +42,7 @@ unsafe extern "llvm-intrinsic" {
 /// Version: v1.0.1
 ///
 /// Section: 3.27
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha256sig0))]
 #[inline]
@@ -65,7 +65,7 @@ pub fn sha256sig0(rs1: u32) -> u32 {
 /// Version: v1.0.1
 ///
 /// Section: 3.28
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha256sig1))]
 #[inline]
@@ -88,7 +88,7 @@ pub fn sha256sig1(rs1: u32) -> u32 {
 /// Version: v1.0.1
 ///
 /// Section: 3.29
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha256sum0))]
 #[inline]
@@ -111,7 +111,7 @@ pub fn sha256sum0(rs1: u32) -> u32 {
 /// Version: v1.0.1
 ///
 /// Section: 3.30
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha256sum1))]
 #[inline]
@@ -184,7 +184,7 @@ pub fn sha256sum1(rs1: u32) -> u32 {
 /// return c3; // c3 represents c[0..=3]
 /// # }
 /// ```
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zksed")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(sm4ed, BS = 0))]
@@ -260,7 +260,7 @@ pub fn sm4ed<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
 /// return c3; // c3 represents c[0..=3]
 /// # }
 /// ```
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zksed")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(sm4ks, BS = 0))]
@@ -298,7 +298,7 @@ pub fn sm4ks<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
 /// In the SM3 algorithm, the `P0` transformation is used as `E ← P0(TT2)` when the
 /// compression function `CF` uses the intermediate value `TT2` to calculate
 /// the variable `E` in one iteration for subsequent processes.
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zksh")]
 #[cfg_attr(test, assert_instr(sm3p0))]
 #[inline]
@@ -339,7 +339,7 @@ pub fn sm3p0(rs1: u32) -> u32 {
 ///     Wj ← P1(Wj−16 ⊕ Wj−9 ⊕ (Wj−3 ≪ 15)) ⊕ (Wj−13 ≪ 7) ⊕ Wj−6
 /// ENDFOR
 /// ```
-#[stable(feature = "riscv_zk_intrinsics", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_riscv_zk", since = "CURRENT_RUSTC_VERSION")]
 #[target_feature(enable = "zksh")]
 #[cfg_attr(test, assert_instr(sm3p1))]
 #[inline]

From 303f84bb705c2e4dba4991450dd9d0f03293fad4 Mon Sep 17 00:00:00 2001
From: TechnoPorg <mail@technop.org>
Date: Mon, 12 Oct 2026 11:04:20 -0400
Subject: [PATCH 6/6] fix: module stability pt. 2

---
 crates/core_arch/src/mod.rs | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/crates/core_arch/src/mod.rs b/crates/core_arch/src/mod.rs
index edad99ecbb..183af2e2b7 100644
--- a/crates/core_arch/src/mod.rs
+++ b/crates/core_arch/src/mod.rs
@@ -85,7 +85,9 @@ pub mod arch {
     #[doc(cfg(any(target_arch = "riscv32")))]
     #[stable(feature = "stdarch_riscv", since = "CURRENT_RUSTC_VERSION")]
     pub mod riscv32 {
+        #[stable(feature = "stdarch_riscv", since = "CURRENT_RUSTC_VERSION")]
         pub use crate::core_arch::riscv_shared::*;
+        #[stable(feature = "stdarch_riscv", since = "CURRENT_RUSTC_VERSION")]
         pub use crate::core_arch::riscv32::*;
     }
 
@@ -96,10 +98,12 @@ pub mod arch {
     #[doc(cfg(any(target_arch = "riscv64")))]
     #[stable(feature = "stdarch_riscv", since = "CURRENT_RUSTC_VERSION")]
     pub mod riscv64 {
+        #[stable(feature = "stdarch_riscv", since = "CURRENT_RUSTC_VERSION")]
         pub use crate::core_arch::riscv64::*;
         // RISC-V RV64 supports all RV32 instructions as well in current specifications (2022-01-05).
         // Module `riscv_shared` includes instructions available under all RISC-V platforms,
         // i.e. RISC-V RV32 instructions.
+        #[stable(feature = "stdarch_riscv", since = "CURRENT_RUSTC_VERSION")]
         pub use crate::core_arch::riscv_shared::*;
     }