diff --git a/CI/build/conf/cores_config.json b/CI/build/conf/cores_config.json
index dd46ea0214..f16fdf4827 100644
--- a/CI/build/conf/cores_config.json
+++ b/CI/build/conf/cores_config.json
@@ -590,6 +590,8 @@
"GENERIC_H563RIVX",
"GENERIC_H563ZGTX",
"GENERIC_H563ZITX",
+ "GENERIC_H5E5ZJTX",
+ "GENERIC_H5E5ZKTX",
"GENERIC_H723VEHX",
"GENERIC_H723VETX",
"GENERIC_H723VGHX",
diff --git a/CI/build/conf/cores_config_ci.json b/CI/build/conf/cores_config_ci.json
index eb748b3ce6..0458794a8d 100644
--- a/CI/build/conf/cores_config_ci.json
+++ b/CI/build/conf/cores_config_ci.json
@@ -590,6 +590,8 @@
"GENERIC_H563RIVX",
"GENERIC_H563ZGTX",
"GENERIC_H563ZITX",
+ "GENERIC_H5E5ZJTX",
+ "GENERIC_H5E5ZKTX",
"GENERIC_H723VEHX",
"GENERIC_H723VETX",
"GENERIC_H723VGHX",
diff --git a/README.md b/README.md
index 683d717a8e..9404e80053 100644
--- a/README.md
+++ b/README.md
@@ -114,6 +114,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| :green_heart: | STM32F767ZI | [Nucleo F767ZI](http://www.st.com/en/evaluation-tools/nucleo-f767zi.html) | *1.4.0* | |
| :green_heart: | STM32F746ZG | [Nucleo F746ZG](https://www.st.com/en/evaluation-tools/nucleo-f746zg.html) | *1.9.0* | |
| :green_heart: | STM32F756ZG | [Nucleo F756ZG](https://www.st.com/en/evaluation-tools/nucleo-f756zg.html) | *1.9.0* | |
+| :yellow_heart: | STM32H5E5ZJ | [NUCLEO H5E5ZJ](https://www.st.com/en/evaluation-tools/nucleo-h5e5zj.html) | **3.0.1** | |
| :green_heart: | STM32H563ZI | [Nucleo H563ZI](https://www.st.com/en/evaluation-tools/nucleo-h563zi.html) | *2.6.0* | |
| :green_heart: | STM32H723ZG | [Nucleo H723ZG](https://www.st.com/en/evaluation-tools/nucleo-h723zg.html) | *2.4.0* | |
| :green_heart: | STM32H743ZI | [Nucleo H743ZI(2)](https://www.st.com/en/evaluation-tools/nucleo-h743zi.html) | *1.5.0* | Nucleo H743ZI2 since 1.6.0 |
@@ -593,6 +594,8 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| Status | Device(s) | Name | Release | Notes |
| :----: | :-------: | ---- | :-----: | :---- |
+| :yellow_heart: | STM32H5E5ZJ
STM32H5E5ZK | Generic Board | **3.0.1** | |
+| :yellow_heart: | STM32H5F5ZJ | Generic Board | **3.0.1** | |
| :green_heart: | STM32H503CB | Generic Board | *2.9.0* | |
| :green_heart: | STM32H503KB | Generic Board | *2.8.1* | |
| :green_heart: | STM32H503RB | Generic Board | *2.7.0* | |
diff --git a/boards.txt b/boards.txt
index 9849aa95cb..a4fc43865c 100644
--- a/boards.txt
+++ b/boards.txt
@@ -201,6 +201,22 @@ Nucleo_144.menu.pnum.NUCLEO_F767ZI.build.variant=STM32F7xx/F765Z(G-I)T_F767Z(G-I
Nucleo_144.menu.pnum.NUCLEO_F767ZI.openocd.target=stm32f7x
Nucleo_144.menu.pnum.NUCLEO_F767ZI.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F7xx/STM32F767.svd
+#NUCLEO H5E5ZJ
+Nucleo_144.menu.pnum.NUCLEO_H5E5ZJ=Nucleo H5E5ZJ
+Nucleo_144.menu.pnum.NUCLEO_H5E5ZJ.node=NOD_H5E5ZJ
+Nucleo_144.menu.pnum.NUCLEO_H5E5ZJ.upload.maximum_size=4194304
+Nucleo_144.menu.pnum.NUCLEO_H5E5ZJ.upload.maximum_data_size=1572864
+Nucleo_144.menu.pnum.NUCLEO_H5E5ZJ.build.mcu=cortex-m33
+Nucleo_144.menu.pnum.NUCLEO_H5E5ZJ.build.fpu=-mfpu=fpv5-sp-d16
+Nucleo_144.menu.pnum.NUCLEO_H5E5ZJ.build.float-abi=-mfloat-abi=hard
+Nucleo_144.menu.pnum.NUCLEO_H5E5ZJ.build.board=NUCLEO_H5E5ZJ
+Nucleo_144.menu.pnum.NUCLEO_H5E5ZJ.build.series=STM32H5xx
+Nucleo_144.menu.pnum.NUCLEO_H5E5ZJ.build.product_line=STM32H5E5xx
+Nucleo_144.menu.pnum.NUCLEO_H5E5ZJ.build.variant=STM32H5xx/H5E5Z(J-K)T_H5F5ZJT
+Nucleo_144.menu.pnum.NUCLEO_H5E5ZJ.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS
+Nucleo_144.menu.pnum.NUCLEO_H5E5ZJ.openocd.target=stm32h5x
+Nucleo_144.menu.pnum.NUCLEO_H5E5ZJ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H5E5.svd
+
# NUCLEO H563ZI
Nucleo_144.menu.pnum.NUCLEO_H563ZI=Nucleo H563ZI
Nucleo_144.menu.pnum.NUCLEO_H563ZI.node=NOD_H563ZI
@@ -9486,6 +9502,33 @@ GenH5.menu.pnum.WEACT_H562RG.build.variant_h=variant_WEACT_H562RG.h
GenH5.menu.pnum.WEACT_H562RG.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS
GenH5.menu.pnum.WEACT_H562RG.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H562.svd
+# Generic H5E5ZJTx
+GenH5.menu.pnum.GENERIC_H5E5ZJTX=Generic H5E5ZJTx
+GenH5.menu.pnum.GENERIC_H5E5ZJTX.upload.maximum_size=4194304
+GenH5.menu.pnum.GENERIC_H5E5ZJTX.upload.maximum_data_size=1572864
+GenH5.menu.pnum.GENERIC_H5E5ZJTX.build.board=GENERIC_H5E5ZJTX
+GenH5.menu.pnum.GENERIC_H5E5ZJTX.build.product_line=STM32H5E5xx
+GenH5.menu.pnum.GENERIC_H5E5ZJTX.build.variant=STM32H5xx/H5E5Z(J-K)T_H5F5ZJT
+GenH5.menu.pnum.GENERIC_H5E5ZJTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H5E5.svd
+
+# Generic H5E5ZKTx
+GenH5.menu.pnum.GENERIC_H5E5ZKTX=Generic H5E5ZKTx
+GenH5.menu.pnum.GENERIC_H5E5ZKTX.upload.maximum_size=3145728
+GenH5.menu.pnum.GENERIC_H5E5ZKTX.upload.maximum_data_size=1572864
+GenH5.menu.pnum.GENERIC_H5E5ZKTX.build.board=GENERIC_H5E5ZKTX
+GenH5.menu.pnum.GENERIC_H5E5ZKTX.build.product_line=STM32H5E5xx
+GenH5.menu.pnum.GENERIC_H5E5ZKTX.build.variant=STM32H5xx/H5E5Z(J-K)T_H5F5ZJT
+GenH5.menu.pnum.GENERIC_H5E5ZKTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H5E5.svd
+
+# Generic H5F5ZJTx
+GenH5.menu.pnum.GENERIC_H5F5ZJTX=Generic H5F5ZJTx
+GenH5.menu.pnum.GENERIC_H5F5ZJTX.upload.maximum_size=4194304
+GenH5.menu.pnum.GENERIC_H5F5ZJTX.upload.maximum_data_size=1572864
+GenH5.menu.pnum.GENERIC_H5F5ZJTX.build.board=GENERIC_H5F5ZJTX
+GenH5.menu.pnum.GENERIC_H5F5ZJTX.build.product_line=STM32H5F5xx
+GenH5.menu.pnum.GENERIC_H5F5ZJTX.build.variant=STM32H5xx/H5E5Z(J-K)T_H5F5ZJT
+GenH5.menu.pnum.GENERIC_H5F5ZJTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H5F5.svd
+
# Generic H503CBTx
GenH5.menu.pnum.GENERIC_H503CBTX=Generic H503CBTx
GenH5.menu.pnum.GENERIC_H503CBTX.upload.maximum_size=131072
diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake
index d5abe02ead..5371b78a12 100644
--- a/cmake/boards_db.cmake
+++ b/cmake/boards_db.cmake
@@ -75903,6 +75903,243 @@ target_compile_options(GENERIC_H573ZITX_xusb_HSFS INTERFACE
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
)
+# GENERIC_H5E5ZJTX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_H5E5ZJTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H5E5Z(J-K)T_H5F5ZJT")
+set(GENERIC_H5E5ZJTX_MAXSIZE 4194304)
+set(GENERIC_H5E5ZJTX_MAXDATASIZE 1572864)
+set(GENERIC_H5E5ZJTX_MCU cortex-m33)
+set(GENERIC_H5E5ZJTX_FPCONF "-")
+add_library(GENERIC_H5E5ZJTX INTERFACE)
+target_compile_options(GENERIC_H5E5ZJTX INTERFACE
+ "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER"
+ "SHELL:-DSTM32H5E5xx"
+ "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_H5E5ZJTX_MCU}
+)
+target_compile_definitions(GENERIC_H5E5ZJTX INTERFACE
+ "STM32H5xx"
+ "ARDUINO_GENERIC_H5E5ZJTX"
+ "BOARD_NAME=\"GENERIC_H5E5ZJTX\""
+ "BOARD_ID=GENERIC_H5E5ZJTX"
+ "VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_H5E5ZJTX INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H5xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/
+ ${GENERIC_H5E5ZJTX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_H5E5ZJTX INTERFACE
+ "LINKER:--default-script=${GENERIC_H5E5ZJTX_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=4194304"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=1572864"
+ "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_H5E5ZJTX_MCU}
+)
+
+add_library(GENERIC_H5E5ZJTX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_H5E5ZJTX_serial_disabled INTERFACE
+)
+add_library(GENERIC_H5E5ZJTX_serial_generic INTERFACE)
+target_compile_options(GENERIC_H5E5ZJTX_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_H5E5ZJTX_serial_none INTERFACE)
+target_compile_options(GENERIC_H5E5ZJTX_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_H5E5ZJTX_usb_CDC INTERFACE)
+target_compile_options(GENERIC_H5E5ZJTX_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_H5E5ZJTX_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_H5E5ZJTX_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_H5E5ZJTX_usb_HID INTERFACE)
+target_compile_options(GENERIC_H5E5ZJTX_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_H5E5ZJTX_usb_none INTERFACE)
+target_compile_options(GENERIC_H5E5ZJTX_usb_none INTERFACE
+)
+add_library(GENERIC_H5E5ZJTX_xusb_FS INTERFACE)
+target_compile_options(GENERIC_H5E5ZJTX_xusb_FS INTERFACE
+)
+add_library(GENERIC_H5E5ZJTX_xusb_HS INTERFACE)
+target_compile_options(GENERIC_H5E5ZJTX_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_H5E5ZJTX_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_H5E5ZJTX_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
+# GENERIC_H5E5ZKTX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_H5E5ZKTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H5E5Z(J-K)T_H5F5ZJT")
+set(GENERIC_H5E5ZKTX_MAXSIZE 3145728)
+set(GENERIC_H5E5ZKTX_MAXDATASIZE 1572864)
+set(GENERIC_H5E5ZKTX_MCU cortex-m33)
+set(GENERIC_H5E5ZKTX_FPCONF "-")
+add_library(GENERIC_H5E5ZKTX INTERFACE)
+target_compile_options(GENERIC_H5E5ZKTX INTERFACE
+ "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER"
+ "SHELL:-DSTM32H5E5xx"
+ "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_H5E5ZKTX_MCU}
+)
+target_compile_definitions(GENERIC_H5E5ZKTX INTERFACE
+ "STM32H5xx"
+ "ARDUINO_GENERIC_H5E5ZKTX"
+ "BOARD_NAME=\"GENERIC_H5E5ZKTX\""
+ "BOARD_ID=GENERIC_H5E5ZKTX"
+ "VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_H5E5ZKTX INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H5xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/
+ ${GENERIC_H5E5ZKTX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_H5E5ZKTX INTERFACE
+ "LINKER:--default-script=${GENERIC_H5E5ZKTX_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=3145728"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=1572864"
+ "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_H5E5ZKTX_MCU}
+)
+
+add_library(GENERIC_H5E5ZKTX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_H5E5ZKTX_serial_disabled INTERFACE
+)
+add_library(GENERIC_H5E5ZKTX_serial_generic INTERFACE)
+target_compile_options(GENERIC_H5E5ZKTX_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_H5E5ZKTX_serial_none INTERFACE)
+target_compile_options(GENERIC_H5E5ZKTX_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_H5E5ZKTX_usb_CDC INTERFACE)
+target_compile_options(GENERIC_H5E5ZKTX_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_H5E5ZKTX_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_H5E5ZKTX_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_H5E5ZKTX_usb_HID INTERFACE)
+target_compile_options(GENERIC_H5E5ZKTX_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_H5E5ZKTX_usb_none INTERFACE)
+target_compile_options(GENERIC_H5E5ZKTX_usb_none INTERFACE
+)
+add_library(GENERIC_H5E5ZKTX_xusb_FS INTERFACE)
+target_compile_options(GENERIC_H5E5ZKTX_xusb_FS INTERFACE
+)
+add_library(GENERIC_H5E5ZKTX_xusb_HS INTERFACE)
+target_compile_options(GENERIC_H5E5ZKTX_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_H5E5ZKTX_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_H5E5ZKTX_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
+# GENERIC_H5F5ZJTX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_H5F5ZJTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H5E5Z(J-K)T_H5F5ZJT")
+set(GENERIC_H5F5ZJTX_MAXSIZE 4194304)
+set(GENERIC_H5F5ZJTX_MAXDATASIZE 1572864)
+set(GENERIC_H5F5ZJTX_MCU cortex-m33)
+set(GENERIC_H5F5ZJTX_FPCONF "-")
+add_library(GENERIC_H5F5ZJTX INTERFACE)
+target_compile_options(GENERIC_H5F5ZJTX INTERFACE
+ "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER"
+ "SHELL:-DSTM32H5F5xx"
+ "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_H5F5ZJTX_MCU}
+)
+target_compile_definitions(GENERIC_H5F5ZJTX INTERFACE
+ "STM32H5xx"
+ "ARDUINO_GENERIC_H5F5ZJTX"
+ "BOARD_NAME=\"GENERIC_H5F5ZJTX\""
+ "BOARD_ID=GENERIC_H5F5ZJTX"
+ "VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_H5F5ZJTX INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H5xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/
+ ${GENERIC_H5F5ZJTX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_H5F5ZJTX INTERFACE
+ "LINKER:--default-script=${GENERIC_H5F5ZJTX_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=4194304"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=1572864"
+ "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_H5F5ZJTX_MCU}
+)
+
+add_library(GENERIC_H5F5ZJTX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_H5F5ZJTX_serial_disabled INTERFACE
+)
+add_library(GENERIC_H5F5ZJTX_serial_generic INTERFACE)
+target_compile_options(GENERIC_H5F5ZJTX_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_H5F5ZJTX_serial_none INTERFACE)
+target_compile_options(GENERIC_H5F5ZJTX_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_H5F5ZJTX_usb_CDC INTERFACE)
+target_compile_options(GENERIC_H5F5ZJTX_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_H5F5ZJTX_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_H5F5ZJTX_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_H5F5ZJTX_usb_HID INTERFACE)
+target_compile_options(GENERIC_H5F5ZJTX_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_H5F5ZJTX_usb_none INTERFACE)
+target_compile_options(GENERIC_H5F5ZJTX_usb_none INTERFACE
+)
+add_library(GENERIC_H5F5ZJTX_xusb_FS INTERFACE)
+target_compile_options(GENERIC_H5F5ZJTX_xusb_FS INTERFACE
+)
+add_library(GENERIC_H5F5ZJTX_xusb_HS INTERFACE)
+target_compile_options(GENERIC_H5F5ZJTX_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_H5F5ZJTX_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_H5F5ZJTX_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
# GENERIC_H723VEHX
# -----------------------------------------------------------------------------
@@ -109600,6 +109837,86 @@ target_compile_options(NUCLEO_H563ZI_xusb_HSFS INTERFACE
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
)
+# NUCLEO_H5E5ZJ
+# -----------------------------------------------------------------------------
+
+set(NUCLEO_H5E5ZJ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H5E5Z(J-K)T_H5F5ZJT")
+set(NUCLEO_H5E5ZJ_MAXSIZE 4194304)
+set(NUCLEO_H5E5ZJ_MAXDATASIZE 1572864)
+set(NUCLEO_H5E5ZJ_MCU cortex-m33)
+set(NUCLEO_H5E5ZJ_FPCONF "fpv5-sp-d16-hard")
+add_library(NUCLEO_H5E5ZJ INTERFACE)
+target_compile_options(NUCLEO_H5E5ZJ INTERFACE
+ "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER"
+ "SHELL:-DSTM32H5E5xx"
+ "SHELL:-DCUSTOM_PERIPHERAL_PINS"
+ "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard"
+ -mcpu=${NUCLEO_H5E5ZJ_MCU}
+)
+target_compile_definitions(NUCLEO_H5E5ZJ INTERFACE
+ "STM32H5xx"
+ "ARDUINO_NUCLEO_H5E5ZJ"
+ "BOARD_NAME=\"NUCLEO_H5E5ZJ\""
+ "BOARD_ID=NUCLEO_H5E5ZJ"
+ "VARIANT_H=\"variant_NUCLEO_H5E5ZJ.h\""
+)
+target_include_directories(NUCLEO_H5E5ZJ INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H5xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/
+ ${NUCLEO_H5E5ZJ_VARIANT_PATH}
+)
+
+target_link_options(NUCLEO_H5E5ZJ INTERFACE
+ "LINKER:--default-script=${NUCLEO_H5E5ZJ_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=4194304"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=1572864"
+ "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard"
+ -mcpu=${NUCLEO_H5E5ZJ_MCU}
+)
+
+add_library(NUCLEO_H5E5ZJ_serial_disabled INTERFACE)
+target_compile_options(NUCLEO_H5E5ZJ_serial_disabled INTERFACE
+)
+add_library(NUCLEO_H5E5ZJ_serial_generic INTERFACE)
+target_compile_options(NUCLEO_H5E5ZJ_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(NUCLEO_H5E5ZJ_serial_none INTERFACE)
+target_compile_options(NUCLEO_H5E5ZJ_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(NUCLEO_H5E5ZJ_usb_CDC INTERFACE)
+target_compile_options(NUCLEO_H5E5ZJ_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(NUCLEO_H5E5ZJ_usb_CDCgen INTERFACE)
+target_compile_options(NUCLEO_H5E5ZJ_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(NUCLEO_H5E5ZJ_usb_HID INTERFACE)
+target_compile_options(NUCLEO_H5E5ZJ_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(NUCLEO_H5E5ZJ_usb_none INTERFACE)
+target_compile_options(NUCLEO_H5E5ZJ_usb_none INTERFACE
+)
+add_library(NUCLEO_H5E5ZJ_xusb_FS INTERFACE)
+target_compile_options(NUCLEO_H5E5ZJ_xusb_FS INTERFACE
+)
+add_library(NUCLEO_H5E5ZJ_xusb_HS INTERFACE)
+target_compile_options(NUCLEO_H5E5ZJ_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(NUCLEO_H5E5ZJ_xusb_HSFS INTERFACE)
+target_compile_options(NUCLEO_H5E5ZJ_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
# NUCLEO_H723ZG
# -----------------------------------------------------------------------------
diff --git a/libraries/USBDevice/src/usbd_conf.c b/libraries/USBDevice/src/usbd_conf.c
index 85398b8bea..a5f216e5a8 100644
--- a/libraries/USBDevice/src/usbd_conf.c
+++ b/libraries/USBDevice/src/usbd_conf.c
@@ -152,7 +152,7 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
#ifdef __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
__HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT();
#endif
-#if !defined(STM32L4xx) && !defined(STM32U5xx)
+#if !defined(STM32H5xx) && !defined(STM32L4xx) && !defined(STM32U5xx)
/* Set EXTI Wakeup Interrupt priority */
HAL_NVIC_SetPriority(OTG_FS_WKUP_IRQn, USBD_IRQ_PRIO, USBD_IRQ_SUBPRIO);
@@ -170,7 +170,7 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
pin_function(map->pin, map->function);
map++;
}
-#ifndef USE_USB_HS_IN_FS
+#if !defined(USE_USB_HS_IN_FS) && defined(__HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE)
__HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE();
#endif /* USE_USB_HS_IN_FS */
/* Enable USB HS Clocks */
@@ -183,6 +183,16 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
#endif
#ifdef SYSCFG_OTGHSPHYCR_EN
HAL_SYSCFG_EnableOTGPHY(SYSCFG_OTG_HS_PHY_ENABLE);
+#endif
+#if defined(RCC_AHB2ENR_OTGPHYEN)
+ /* STM32H5E/F specific PHY initialization */
+ __HAL_RCC_OTGPHY_CLK_ENABLE();
+ /* Adjust the disconnect threshold and the squelch threshold */
+ /* Recommended values */
+ HAL_SBS_SetOTGPHYDisconnectThreshold(SBS_OTG_HS_PHY_DISCONNECT_5_9PERCENT);
+ HAL_SBS_SetOTGPHYSquelchThreshold(SBS_OTG_HS_PHY_SQUELCH_15PERCENT);
+ /* Enable the OTG_HS PHY */
+ HAL_PWREx_EnableUSBOTGHSPhy();
#endif
/* Set USB HS Interrupt priority */
HAL_NVIC_SetPriority(OTG_HS_IRQn, USBD_IRQ_PRIO, USBD_IRQ_SUBPRIO);
diff --git a/variants/STM32H5xx/H5E4A(J-K)I_H5F4AJI/CMakeLists.txt b/variants/STM32H5xx/H5E4A(J-K)I_H5F4AJI/CMakeLists.txt
new file mode 100644
index 0000000000..2a4d55b6b1
--- /dev/null
+++ b/variants/STM32H5xx/H5E4A(J-K)I_H5F4AJI/CMakeLists.txt
@@ -0,0 +1,31 @@
+# v3.21 implemented semantic changes regarding $
+# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects
+cmake_minimum_required(VERSION 3.21)
+
+add_library(variant INTERFACE)
+add_library(variant_usage INTERFACE)
+
+target_include_directories(variant_usage INTERFACE
+ .
+)
+
+
+target_link_libraries(variant_usage INTERFACE
+ base_config
+)
+
+target_link_libraries(variant INTERFACE variant_usage)
+
+
+
+add_library(variant_bin STATIC EXCLUDE_FROM_ALL
+ generic_clock.c
+ PeripheralPins.c
+ variant_generic.cpp
+)
+target_link_libraries(variant_bin PUBLIC variant_usage)
+
+target_link_libraries(variant INTERFACE
+ variant_bin
+)
+
diff --git a/variants/STM32H5xx/H5E4AJIxQ_H5F4AJIxQ/CMakeLists.txt b/variants/STM32H5xx/H5E4AJIxQ_H5F4AJIxQ/CMakeLists.txt
new file mode 100644
index 0000000000..2a4d55b6b1
--- /dev/null
+++ b/variants/STM32H5xx/H5E4AJIxQ_H5F4AJIxQ/CMakeLists.txt
@@ -0,0 +1,31 @@
+# v3.21 implemented semantic changes regarding $
+# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects
+cmake_minimum_required(VERSION 3.21)
+
+add_library(variant INTERFACE)
+add_library(variant_usage INTERFACE)
+
+target_include_directories(variant_usage INTERFACE
+ .
+)
+
+
+target_link_libraries(variant_usage INTERFACE
+ base_config
+)
+
+target_link_libraries(variant INTERFACE variant_usage)
+
+
+
+add_library(variant_bin STATIC EXCLUDE_FROM_ALL
+ generic_clock.c
+ PeripheralPins.c
+ variant_generic.cpp
+)
+target_link_libraries(variant_bin PUBLIC variant_usage)
+
+target_link_libraries(variant INTERFACE
+ variant_bin
+)
+
diff --git a/variants/STM32H5xx/H5E4I(J-K)(K-T)_H5F4IJ(K-T)/CMakeLists.txt b/variants/STM32H5xx/H5E4I(J-K)(K-T)_H5F4IJ(K-T)/CMakeLists.txt
new file mode 100644
index 0000000000..2a4d55b6b1
--- /dev/null
+++ b/variants/STM32H5xx/H5E4I(J-K)(K-T)_H5F4IJ(K-T)/CMakeLists.txt
@@ -0,0 +1,31 @@
+# v3.21 implemented semantic changes regarding $
+# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects
+cmake_minimum_required(VERSION 3.21)
+
+add_library(variant INTERFACE)
+add_library(variant_usage INTERFACE)
+
+target_include_directories(variant_usage INTERFACE
+ .
+)
+
+
+target_link_libraries(variant_usage INTERFACE
+ base_config
+)
+
+target_link_libraries(variant INTERFACE variant_usage)
+
+
+
+add_library(variant_bin STATIC EXCLUDE_FROM_ALL
+ generic_clock.c
+ PeripheralPins.c
+ variant_generic.cpp
+)
+target_link_libraries(variant_bin PUBLIC variant_usage)
+
+target_link_libraries(variant INTERFACE
+ variant_bin
+)
+
diff --git a/variants/STM32H5xx/H5E4IJKxQ_H5F4IJKxQ/CMakeLists.txt b/variants/STM32H5xx/H5E4IJKxQ_H5F4IJKxQ/CMakeLists.txt
new file mode 100644
index 0000000000..2a4d55b6b1
--- /dev/null
+++ b/variants/STM32H5xx/H5E4IJKxQ_H5F4IJKxQ/CMakeLists.txt
@@ -0,0 +1,31 @@
+# v3.21 implemented semantic changes regarding $
+# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects
+cmake_minimum_required(VERSION 3.21)
+
+add_library(variant INTERFACE)
+add_library(variant_usage INTERFACE)
+
+target_include_directories(variant_usage INTERFACE
+ .
+)
+
+
+target_link_libraries(variant_usage INTERFACE
+ base_config
+)
+
+target_link_libraries(variant INTERFACE variant_usage)
+
+
+
+add_library(variant_bin STATIC EXCLUDE_FROM_ALL
+ generic_clock.c
+ PeripheralPins.c
+ variant_generic.cpp
+)
+target_link_libraries(variant_bin PUBLIC variant_usage)
+
+target_link_libraries(variant INTERFACE
+ variant_bin
+)
+
diff --git a/variants/STM32H5xx/H5E4IJTxQ_H5F4IJTxQ/CMakeLists.txt b/variants/STM32H5xx/H5E4IJTxQ_H5F4IJTxQ/CMakeLists.txt
new file mode 100644
index 0000000000..2a4d55b6b1
--- /dev/null
+++ b/variants/STM32H5xx/H5E4IJTxQ_H5F4IJTxQ/CMakeLists.txt
@@ -0,0 +1,31 @@
+# v3.21 implemented semantic changes regarding $
+# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects
+cmake_minimum_required(VERSION 3.21)
+
+add_library(variant INTERFACE)
+add_library(variant_usage INTERFACE)
+
+target_include_directories(variant_usage INTERFACE
+ .
+)
+
+
+target_link_libraries(variant_usage INTERFACE
+ base_config
+)
+
+target_link_libraries(variant INTERFACE variant_usage)
+
+
+
+add_library(variant_bin STATIC EXCLUDE_FROM_ALL
+ generic_clock.c
+ PeripheralPins.c
+ variant_generic.cpp
+)
+target_link_libraries(variant_bin PUBLIC variant_usage)
+
+target_link_libraries(variant INTERFACE
+ variant_bin
+)
+
diff --git a/variants/STM32H5xx/H5E4V(J-K)T_H5F4VJT/CMakeLists.txt b/variants/STM32H5xx/H5E4V(J-K)T_H5F4VJT/CMakeLists.txt
new file mode 100644
index 0000000000..2a4d55b6b1
--- /dev/null
+++ b/variants/STM32H5xx/H5E4V(J-K)T_H5F4VJT/CMakeLists.txt
@@ -0,0 +1,31 @@
+# v3.21 implemented semantic changes regarding $
+# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects
+cmake_minimum_required(VERSION 3.21)
+
+add_library(variant INTERFACE)
+add_library(variant_usage INTERFACE)
+
+target_include_directories(variant_usage INTERFACE
+ .
+)
+
+
+target_link_libraries(variant_usage INTERFACE
+ base_config
+)
+
+target_link_libraries(variant INTERFACE variant_usage)
+
+
+
+add_library(variant_bin STATIC EXCLUDE_FROM_ALL
+ generic_clock.c
+ PeripheralPins.c
+ variant_generic.cpp
+)
+target_link_libraries(variant_bin PUBLIC variant_usage)
+
+target_link_libraries(variant INTERFACE
+ variant_bin
+)
+
diff --git a/variants/STM32H5xx/H5E4VJTxQ_H5F4VJTxQ/CMakeLists.txt b/variants/STM32H5xx/H5E4VJTxQ_H5F4VJTxQ/CMakeLists.txt
new file mode 100644
index 0000000000..2a4d55b6b1
--- /dev/null
+++ b/variants/STM32H5xx/H5E4VJTxQ_H5F4VJTxQ/CMakeLists.txt
@@ -0,0 +1,31 @@
+# v3.21 implemented semantic changes regarding $
+# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects
+cmake_minimum_required(VERSION 3.21)
+
+add_library(variant INTERFACE)
+add_library(variant_usage INTERFACE)
+
+target_include_directories(variant_usage INTERFACE
+ .
+)
+
+
+target_link_libraries(variant_usage INTERFACE
+ base_config
+)
+
+target_link_libraries(variant INTERFACE variant_usage)
+
+
+
+add_library(variant_bin STATIC EXCLUDE_FROM_ALL
+ generic_clock.c
+ PeripheralPins.c
+ variant_generic.cpp
+)
+target_link_libraries(variant_bin PUBLIC variant_usage)
+
+target_link_libraries(variant INTERFACE
+ variant_bin
+)
+
diff --git a/variants/STM32H5xx/H5E4Z(J-K)J_H5F4ZJJ/CMakeLists.txt b/variants/STM32H5xx/H5E4Z(J-K)J_H5F4ZJJ/CMakeLists.txt
new file mode 100644
index 0000000000..2a4d55b6b1
--- /dev/null
+++ b/variants/STM32H5xx/H5E4Z(J-K)J_H5F4ZJJ/CMakeLists.txt
@@ -0,0 +1,31 @@
+# v3.21 implemented semantic changes regarding $
+# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects
+cmake_minimum_required(VERSION 3.21)
+
+add_library(variant INTERFACE)
+add_library(variant_usage INTERFACE)
+
+target_include_directories(variant_usage INTERFACE
+ .
+)
+
+
+target_link_libraries(variant_usage INTERFACE
+ base_config
+)
+
+target_link_libraries(variant INTERFACE variant_usage)
+
+
+
+add_library(variant_bin STATIC EXCLUDE_FROM_ALL
+ generic_clock.c
+ PeripheralPins.c
+ variant_generic.cpp
+)
+target_link_libraries(variant_bin PUBLIC variant_usage)
+
+target_link_libraries(variant INTERFACE
+ variant_bin
+)
+
diff --git a/variants/STM32H5xx/H5E4Z(J-K)T_H5F4ZJT/CMakeLists.txt b/variants/STM32H5xx/H5E4Z(J-K)T_H5F4ZJT/CMakeLists.txt
new file mode 100644
index 0000000000..2a4d55b6b1
--- /dev/null
+++ b/variants/STM32H5xx/H5E4Z(J-K)T_H5F4ZJT/CMakeLists.txt
@@ -0,0 +1,31 @@
+# v3.21 implemented semantic changes regarding $
+# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects
+cmake_minimum_required(VERSION 3.21)
+
+add_library(variant INTERFACE)
+add_library(variant_usage INTERFACE)
+
+target_include_directories(variant_usage INTERFACE
+ .
+)
+
+
+target_link_libraries(variant_usage INTERFACE
+ base_config
+)
+
+target_link_libraries(variant INTERFACE variant_usage)
+
+
+
+add_library(variant_bin STATIC EXCLUDE_FROM_ALL
+ generic_clock.c
+ PeripheralPins.c
+ variant_generic.cpp
+)
+target_link_libraries(variant_bin PUBLIC variant_usage)
+
+target_link_libraries(variant INTERFACE
+ variant_bin
+)
+
diff --git a/variants/STM32H5xx/H5E4ZJJxQ_H5F4ZJJxQ/CMakeLists.txt b/variants/STM32H5xx/H5E4ZJJxQ_H5F4ZJJxQ/CMakeLists.txt
new file mode 100644
index 0000000000..2a4d55b6b1
--- /dev/null
+++ b/variants/STM32H5xx/H5E4ZJJxQ_H5F4ZJJxQ/CMakeLists.txt
@@ -0,0 +1,31 @@
+# v3.21 implemented semantic changes regarding $
+# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects
+cmake_minimum_required(VERSION 3.21)
+
+add_library(variant INTERFACE)
+add_library(variant_usage INTERFACE)
+
+target_include_directories(variant_usage INTERFACE
+ .
+)
+
+
+target_link_libraries(variant_usage INTERFACE
+ base_config
+)
+
+target_link_libraries(variant INTERFACE variant_usage)
+
+
+
+add_library(variant_bin STATIC EXCLUDE_FROM_ALL
+ generic_clock.c
+ PeripheralPins.c
+ variant_generic.cpp
+)
+target_link_libraries(variant_bin PUBLIC variant_usage)
+
+target_link_libraries(variant INTERFACE
+ variant_bin
+)
+
diff --git a/variants/STM32H5xx/H5E4ZJTxQ_H5F4ZJTxQ/CMakeLists.txt b/variants/STM32H5xx/H5E4ZJTxQ_H5F4ZJTxQ/CMakeLists.txt
new file mode 100644
index 0000000000..2a4d55b6b1
--- /dev/null
+++ b/variants/STM32H5xx/H5E4ZJTxQ_H5F4ZJTxQ/CMakeLists.txt
@@ -0,0 +1,31 @@
+# v3.21 implemented semantic changes regarding $
+# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects
+cmake_minimum_required(VERSION 3.21)
+
+add_library(variant INTERFACE)
+add_library(variant_usage INTERFACE)
+
+target_include_directories(variant_usage INTERFACE
+ .
+)
+
+
+target_link_libraries(variant_usage INTERFACE
+ base_config
+)
+
+target_link_libraries(variant INTERFACE variant_usage)
+
+
+
+add_library(variant_bin STATIC EXCLUDE_FROM_ALL
+ generic_clock.c
+ PeripheralPins.c
+ variant_generic.cpp
+)
+target_link_libraries(variant_bin PUBLIC variant_usage)
+
+target_link_libraries(variant INTERFACE
+ variant_bin
+)
+
diff --git a/variants/STM32H5xx/H5E5I(J-K)KxQ_H5F5IJKxQ/CMakeLists.txt b/variants/STM32H5xx/H5E5I(J-K)KxQ_H5F5IJKxQ/CMakeLists.txt
new file mode 100644
index 0000000000..2a4d55b6b1
--- /dev/null
+++ b/variants/STM32H5xx/H5E5I(J-K)KxQ_H5F5IJKxQ/CMakeLists.txt
@@ -0,0 +1,31 @@
+# v3.21 implemented semantic changes regarding $
+# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects
+cmake_minimum_required(VERSION 3.21)
+
+add_library(variant INTERFACE)
+add_library(variant_usage INTERFACE)
+
+target_include_directories(variant_usage INTERFACE
+ .
+)
+
+
+target_link_libraries(variant_usage INTERFACE
+ base_config
+)
+
+target_link_libraries(variant INTERFACE variant_usage)
+
+
+
+add_library(variant_bin STATIC EXCLUDE_FROM_ALL
+ generic_clock.c
+ PeripheralPins.c
+ variant_generic.cpp
+)
+target_link_libraries(variant_bin PUBLIC variant_usage)
+
+target_link_libraries(variant INTERFACE
+ variant_bin
+)
+
diff --git a/variants/STM32H5xx/H5E5I(J-K)TxQ_H5F5IJTxQ/CMakeLists.txt b/variants/STM32H5xx/H5E5I(J-K)TxQ_H5F5IJTxQ/CMakeLists.txt
new file mode 100644
index 0000000000..2a4d55b6b1
--- /dev/null
+++ b/variants/STM32H5xx/H5E5I(J-K)TxQ_H5F5IJTxQ/CMakeLists.txt
@@ -0,0 +1,31 @@
+# v3.21 implemented semantic changes regarding $
+# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects
+cmake_minimum_required(VERSION 3.21)
+
+add_library(variant INTERFACE)
+add_library(variant_usage INTERFACE)
+
+target_include_directories(variant_usage INTERFACE
+ .
+)
+
+
+target_link_libraries(variant_usage INTERFACE
+ base_config
+)
+
+target_link_libraries(variant INTERFACE variant_usage)
+
+
+
+add_library(variant_bin STATIC EXCLUDE_FROM_ALL
+ generic_clock.c
+ PeripheralPins.c
+ variant_generic.cpp
+)
+target_link_libraries(variant_bin PUBLIC variant_usage)
+
+target_link_libraries(variant INTERFACE
+ variant_bin
+)
+
diff --git a/variants/STM32H5xx/H5E5L(J-K)HxQ_H5F5LJHxQ/CMakeLists.txt b/variants/STM32H5xx/H5E5L(J-K)HxQ_H5F5LJHxQ/CMakeLists.txt
new file mode 100644
index 0000000000..2a4d55b6b1
--- /dev/null
+++ b/variants/STM32H5xx/H5E5L(J-K)HxQ_H5F5LJHxQ/CMakeLists.txt
@@ -0,0 +1,31 @@
+# v3.21 implemented semantic changes regarding $
+# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects
+cmake_minimum_required(VERSION 3.21)
+
+add_library(variant INTERFACE)
+add_library(variant_usage INTERFACE)
+
+target_include_directories(variant_usage INTERFACE
+ .
+)
+
+
+target_link_libraries(variant_usage INTERFACE
+ base_config
+)
+
+target_link_libraries(variant INTERFACE variant_usage)
+
+
+
+add_library(variant_bin STATIC EXCLUDE_FROM_ALL
+ generic_clock.c
+ PeripheralPins.c
+ variant_generic.cpp
+)
+target_link_libraries(variant_bin PUBLIC variant_usage)
+
+target_link_libraries(variant INTERFACE
+ variant_bin
+)
+
diff --git a/variants/STM32H5xx/H5E5V(J-K)YxQ_H5F5VJYxQ/CMakeLists.txt b/variants/STM32H5xx/H5E5V(J-K)YxQ_H5F5VJYxQ/CMakeLists.txt
new file mode 100644
index 0000000000..2a4d55b6b1
--- /dev/null
+++ b/variants/STM32H5xx/H5E5V(J-K)YxQ_H5F5VJYxQ/CMakeLists.txt
@@ -0,0 +1,31 @@
+# v3.21 implemented semantic changes regarding $
+# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects
+cmake_minimum_required(VERSION 3.21)
+
+add_library(variant INTERFACE)
+add_library(variant_usage INTERFACE)
+
+target_include_directories(variant_usage INTERFACE
+ .
+)
+
+
+target_link_libraries(variant_usage INTERFACE
+ base_config
+)
+
+target_link_libraries(variant INTERFACE variant_usage)
+
+
+
+add_library(variant_bin STATIC EXCLUDE_FROM_ALL
+ generic_clock.c
+ PeripheralPins.c
+ variant_generic.cpp
+)
+target_link_libraries(variant_bin PUBLIC variant_usage)
+
+target_link_libraries(variant INTERFACE
+ variant_bin
+)
+
diff --git a/variants/STM32H5xx/H5E5Z(J-K)T_H5F5ZJT/CMakeLists.txt b/variants/STM32H5xx/H5E5Z(J-K)T_H5F5ZJT/CMakeLists.txt
new file mode 100644
index 0000000000..dc6fae0af0
--- /dev/null
+++ b/variants/STM32H5xx/H5E5Z(J-K)T_H5F5ZJT/CMakeLists.txt
@@ -0,0 +1,33 @@
+# v3.21 implemented semantic changes regarding $
+# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects
+cmake_minimum_required(VERSION 3.21)
+
+add_library(variant INTERFACE)
+add_library(variant_usage INTERFACE)
+
+target_include_directories(variant_usage INTERFACE
+ .
+)
+
+
+target_link_libraries(variant_usage INTERFACE
+ base_config
+)
+
+target_link_libraries(variant INTERFACE variant_usage)
+
+
+
+add_library(variant_bin STATIC EXCLUDE_FROM_ALL
+ generic_clock.c
+ PeripheralPins.c
+ PeripheralPins_NUCLEO_H5E5ZJ.c
+ variant_generic.cpp
+ variant_NUCLEO_H5E5ZJ.cpp
+)
+target_link_libraries(variant_bin PUBLIC variant_usage)
+
+target_link_libraries(variant INTERFACE
+ variant_bin
+)
+
diff --git a/variants/STM32H5xx/H5E5Z(J-K)T_H5F5ZJT/PeripheralPins_NUCLEO_H5E5ZJ.c b/variants/STM32H5xx/H5E5Z(J-K)T_H5F5ZJT/PeripheralPins_NUCLEO_H5E5ZJ.c
new file mode 100644
index 0000000000..db1b6bfd84
--- /dev/null
+++ b/variants/STM32H5xx/H5E5Z(J-K)T_H5F5ZJT/PeripheralPins_NUCLEO_H5E5ZJ.c
@@ -0,0 +1,925 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020-2026, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+/*
+ * Automatically generated from STM32H5E5ZJTx.xml, STM32H5E5ZKTx.xml
+ * STM32H5F5ZJTx.xml
+ * CubeMX DB release 6.0.180
+ */
+#if defined(ARDUINO_NUCLEO_H5E5ZJ)
+#include "Arduino.h"
+#include "PeripheralPins.h"
+
+/* =====
+ * Notes:
+ * - The pins mentioned Px_y_ALTz are alternative possibilities which use other
+ * HW peripheral instances. You can use them the same way as any other "normal"
+ * pin (i.e. analogWrite(PA7_ALT1, 128);).
+ *
+ * - Commented lines are alternative possibilities which are not used per default.
+ * If you change them, you will have to know what you do
+ * =====
+ */
+
+//*** ADC ***
+
+#ifdef HAL_ADC_MODULE_ENABLED
+WEAK const PinMap PinMap_ADC[] = {
+ {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_INP0
+ {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_INP0
+ // {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_INP1
+ // {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_INP1
+ // {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_INP14
+ // {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC2_INP14
+ // {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC1_INP15
+ // {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC2_INP15
+ {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 18, 0)}, // ADC1_INP18
+ {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 18, 0)}, // ADC2_INP18
+ // {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 19, 0)}, // ADC1_INP19
+ // {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 19, 0)}, // ADC2_INP19
+ {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_INP3
+ {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_INP3
+ {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_INP7
+ {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_INP7
+ {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_INP9
+ {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_INP9
+ {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_INP5
+ {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_INP5
+ // {PB_2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC3_INP0
+ // {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_INP10
+ // {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_INP10
+ // {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_INP11
+ // {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC2_INP11
+ {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC1_INP12
+ {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC2_INP12
+ {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_INP13
+ {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC2_INP13
+ // {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_INP4
+ // {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_INP4
+ // {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_INP8
+ // {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_INP8
+ // {PE_7, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC3_INP1
+ {PE_8, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC3_INP2
+ {PE_9, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC3_INP3
+ {PE_10, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC3_INP4
+ {PE_11, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC3_INP5
+ {PE_12, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC3_INP6
+ {PE_13, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC3_INP7
+ {PE_14, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC3_INP8
+ {PE_15, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC3_INP9
+ {PF_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_INP2
+ {PF_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_INP6
+ {PF_13, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_INP2
+ {PF_14, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_INP6
+ {NC, NP, 0}
+};
+#endif
+
+//*** DAC ***
+
+#ifdef HAL_DAC_MODULE_ENABLED
+WEAK const PinMap PinMap_DAC[] = {
+ {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1
+ // {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2
+ {NC, NP, 0}
+};
+#endif
+
+//*** I2C ***
+
+#ifdef HAL_I2C_MODULE_ENABLED
+WEAK const PinMap PinMap_I2C_SDA[] = {
+ {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C2)},
+ {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)},
+ {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF6_I2C4)},
+ // {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)},
+ // {PB_9_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF6_I2C4)},
+ // {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C2)},
+ {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)},
+ {PD_6, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)},
+ {PD_13, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF6_I2C1)},
+ {PD_13_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C4)},
+ // {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C2)},
+ {PF_15, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C4)},
+ {PG_6, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C4)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_I2C_MODULE_ENABLED
+WEAK const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)},
+ {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)},
+ {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF6_I2C4)},
+ // {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)},
+ // {PB_8_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF6_I2C4)},
+ {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C2)},
+ {PD_2, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF6_I2C2)},
+ {PD_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)},
+ {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C4)},
+ {PF_1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C2)},
+ {PF_5, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C4)},
+ {PG_7, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C4)},
+ {NC, NP, 0}
+};
+#endif
+
+//*** I3C ***
+
+#ifdef HAL_I3C_MODULE_ENABLED
+WEAK const PinMap PinMap_I3C_SDA[] = {
+ {PB_3, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C2)},
+ {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)},
+ // {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)},
+ // {PB_12, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF8_I3C2)},
+ {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)},
+ // {PF_0, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C2)},
+ {PF_15, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)},
+ {PG_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_I3C_MODULE_ENABLED
+WEAK const PinMap PinMap_I3C_SCL[] = {
+ {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)},
+ // {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)},
+ {PB_10, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF8_I3C2)},
+ {PD_2, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C2)},
+ {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)},
+ {PF_1, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C2)},
+ {PF_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)},
+ {PG_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)},
+ {NC, NP, 0}
+};
+#endif
+
+//*** TIM ***
+
+#ifdef HAL_TIM_MODULE_ENABLED
+WEAK const PinMap PinMap_TIM[] = {
+ {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+ // {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+ // {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+ // {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N
+ // {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+ {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+ {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1
+ {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+ {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+ {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2
+ // {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ // {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+ {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PA_6_ALT1, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
+ {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+ {PA_7_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1
+ {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ // {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+ {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N
+ {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+ {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N
+ {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N
+ // {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ // {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1
+ // {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+ // {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1
+ {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+ // {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ // {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ // {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+ // {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1
+ {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2
+ {PC_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
+ // {PC_1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
+ {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+ {PC_2_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
+ {PC_2_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1
+ // {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+ // {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N
+ {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
+ {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1
+ {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N
+ {PD_3, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
+ {PD_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N
+ {PD_7, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1
+ {PD_8, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2
+ {PD_9, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM13, 1, 0)}, // TIM13_CH1
+ {PD_10, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM14, 1, 0)}, // TIM14_CH1
+ {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+ {PE_4, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N
+ {PE_5, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1
+ {PE_6, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2
+ {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N
+ {PF_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PF_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+ {PF_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+ {PF_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+ {PF_6, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1
+ {PF_7, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1
+ {PF_8, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
+ {PF_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N
+ {PF_9, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1
+ {PF_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N
+ {PF_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+ {PF_12, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+ {PG_0, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PG_1, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PG_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PG_3, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+ {PG_9, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1
+ {PG_10, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2
+ {PG_15, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1
+ {NC, NP, 0}
+};
+#endif
+
+//*** UART ***
+
+#ifdef HAL_UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_TX[] = {
+ {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)},
+ // {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)},
+ {PA_6, USART11, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART11)},
+ {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)},
+ {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)},
+ {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_UART4)},
+ {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART7)},
+ {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART7)},
+ {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)},
+ {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)},
+ {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)},
+ // {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)},
+ {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)},
+ // {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)},
+ // {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_USART1)},
+ {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)},
+ {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)},
+ {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)},
+ // {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)},
+ {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)},
+ {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)},
+ {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)},
+ {PD_15, UART9, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART9)},
+ {PE_2, UART8, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART8)},
+ {PE_3, USART10, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART10)},
+ {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_UART7)},
+ {PE_8_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_USART2)},
+ {PE_10, UART12, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_UART12)},
+ {PE_11, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART6)},
+ {PF_1, UART9, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART9)},
+ {PF_2, UART12, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_UART12)},
+ {PF_3, USART11, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART11)},
+ {PF_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_UART7)},
+ {PG_1, UART9, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART9)},
+ {PG_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_UART12)},
+ // {PG_12, USART10, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_USART10)},
+ {PG_14, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART6)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_RX[] = {
+ // {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)},
+ // {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)},
+ {PA_7, USART11, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART11)},
+ {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART7)},
+ {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)},
+ {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)},
+ // {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_UART4)},
+ {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART7)},
+ {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)},
+ {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)},
+ {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)},
+ {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)},
+ // {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)},
+ {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)},
+ {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_USART1)},
+ // {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)},
+ {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)},
+ {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)},
+ {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)},
+ {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)},
+ {PD_5, UART8, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART8)},
+ {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)},
+ {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)},
+ {PD_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)},
+ {PD_14, UART9, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART9)},
+ {PE_0, UART8, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART8)},
+ {PE_2, USART10, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART10)},
+ {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_UART7)},
+ {PE_7_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_USART2)},
+ {PE_9, UART12, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_UART12)},
+ {PE_12, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART6)},
+ // {PF_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART9)},
+ {PF_4, USART11, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART11)},
+ {PF_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_UART12)},
+ {PF_6, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_UART7)},
+ {PG_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART9)},
+ {PG_2, UART12, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_UART12)},
+ {PG_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART7)},
+ {PG_9, USART10, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_USART10)},
+ {PG_9_ALT1, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART6)},
+ {PG_11, USART10, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_USART10)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_RTS[] = {
+ // {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)},
+ {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)},
+ {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)},
+ {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)},
+ // {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)},
+ {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)},
+ // {PC_1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART11)},
+ // {PC_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_UART12)},
+ // {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)},
+ {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)},
+ {PD_13, UART9, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART9)},
+ {PD_15, UART8, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART8)},
+ {PE_7, UART12, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_UART12)},
+ {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_UART7)},
+ {PE_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)},
+ {PF_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_UART7)},
+ {PG_11, USART11, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART11)},
+ // {PG_12, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART6)},
+ {PG_14, USART10, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_USART10)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_CTS[] = {
+ {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)},
+ // {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)},
+ // {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)},
+ {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)},
+ {PB_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_UART12)},
+ // {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)},
+ {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)},
+ {PB_15_ALT1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART11)},
+ {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)},
+ {PD_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART9)},
+ {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)},
+ {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)},
+ {PD_14, UART8, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART8)},
+ {PE_8, UART12, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_UART12)},
+ {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_UART7)},
+ {PF_5, USART11, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART11)},
+ {PF_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_UART7)},
+ {PG_13, USART10, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_USART10)},
+ {PG_13_ALT1, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART6)},
+ {PG_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART6)},
+ {NC, NP, 0}
+};
+#endif
+
+//*** SPI ***
+
+#ifdef HAL_SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_MOSI[] = {
+ {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)},
+ {PA_7_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_SPI6)},
+ {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_SPI3)},
+ {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)},
+ {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_SPI3)},
+ {PB_5_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_SPI6)},
+ {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)},
+ // {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)},
+ {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)},
+ {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)},
+ {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI3)},
+ {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)},
+ {PE_6, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)},
+ {PE_14, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)},
+ {PF_9, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI5)},
+ {PF_11, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI5)},
+ {PG_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_SPI2)},
+ {PG_14, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI6)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)},
+ {PA_6_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_SPI6)},
+ {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)},
+ {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)},
+ {PB_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_SPI6)},
+ // {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)},
+ {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)},
+ {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)},
+ // {PE_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)},
+ {PE_13, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)},
+ {PF_8, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI5)},
+ {PF_14, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)},
+ {PG_9, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)},
+ // {PG_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI6)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_SCLK[] = {
+ // {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)},
+ // {PA_5_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_SPI6)},
+ {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)},
+ {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)},
+ {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)},
+ {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)},
+ {PB_3_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_SPI6)},
+ {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)},
+ // {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)},
+ {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)},
+ {PC_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI6)},
+ {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)},
+ {PE_2, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)},
+ {PE_12, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)},
+ {PF_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI5)},
+ {PG_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)},
+ {PG_13, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI6)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_SSEL[] = {
+ {PA_0, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI6)},
+ // {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)},
+ {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)},
+ {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)},
+ {PA_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_SPI6)},
+ // {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)},
+ {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)},
+ {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)},
+ {PA_15_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_SPI6)},
+ {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_SPI2)},
+ // {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)},
+ // {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)},
+ {PE_4, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)},
+ {PE_11, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)},
+ {PF_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI5)},
+ {PG_10, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)},
+ {NC, NP, 0}
+};
+#endif
+
+//*** FDCAN ***
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+WEAK const PinMap PinMap_CAN_RD[] = {
+ // {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)},
+ {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)},
+ // {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)},
+ // {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)},
+ {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)},
+ {PD_9, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)},
+ {PD_10, FDCAN3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN3)},
+ {PE_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)},
+ {PE_13, FDCAN3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN3)},
+ {PF_7, FDCAN3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN3)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+WEAK const PinMap PinMap_CAN_TD[] = {
+ {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)},
+ {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)},
+ {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)},
+ {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)},
+ // {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)},
+ // {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)},
+ // {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)},
+ {PD_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)},
+ {PD_8, FDCAN3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN3)},
+ {PE_12, FDCAN3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN3)},
+ {PF_6, FDCAN3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN3)},
+ {NC, NP, 0}
+};
+#endif
+
+//*** ETHERNET ***
+
+#ifdef HAL_ETH_MODULE_ENABLED
+WEAK const PinMap PinMap_Ethernet[] = {
+ // {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_CRS
+ {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_CLK | ETH_RMII_REF_CLK
+ {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO
+ // {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_COL
+ {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN | ETH_RMII_TX_EN
+ // {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_DV | ETH_RMII_CRS_DV
+ // {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_ER
+ // {PA_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CLK
+ // {PA_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_ETH)}, // ETH_PHY_INTN
+ // {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD2
+ // {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD3
+ // {PB_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD0 | ETH_RMII_RXD0
+ // {PB_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_ETH)}, // ETH_MDC
+ // {PB_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_ETH)}, // ETH_MDIO
+ // {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT
+ // {PB_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_ER
+ // {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD3
+ // {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_ER
+ {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 | ETH_RMII_TXD0
+ // {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 | ETH_RMII_TXD1
+ {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDC
+ // {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD2
+ // {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_CLK
+ {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD0 | ETH_RMII_RXD0
+ {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD1 | ETH_RMII_RXD1
+ // {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 | ETH_RMII_TXD0
+ // {PC_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_ETH)}, // ETH_PPS_OUT
+ {PD_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_DV | ETH_RMII_CRS_DV
+ {PD_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CLK
+ // {PD_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_ETH)}, // ETH_MII_CRS
+ // {PD_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_ETH)}, // ETH_MII_RXD0 | ETH_RMII_RXD0
+ // {PD_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_ETH)}, // ETH_MII_CRS
+ // {PD_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PTP_AUX_TS
+ // {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD3
+ // {PE_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD0 | ETH_RMII_RXD0
+ // {PE_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD1 | ETH_RMII_RXD1
+ // {PE_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO
+ // {PF_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_ER
+ // {PF_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDC
+ // {PF_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CLK
+ // {PG_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_ETH)}, // ETH_MII_RX_ER
+ // {PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN | ETH_RMII_TX_EN
+ {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 | ETH_RMII_TXD1
+ // {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 | ETH_RMII_TXD0
+ // {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 | ETH_RMII_TXD1
+ {NC, NP, 0}
+};
+#endif
+
+//*** OCTOSPI ***
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_OCTOSPI_DATA0[] = {
+ // {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPIM_P1_IO0
+ // {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P1_IO0
+ // {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P1_IO0
+ // {PD_3, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_IO0
+ {PD_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P1_IO0
+ // {PE_3, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_IO0
+ // {PF_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO0
+ // {PG_0, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_IO0
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_OCTOSPI_DATA1[] = {
+ // {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPIM_P1_IO1
+ // {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P1_IO1
+ // {PD_2, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P2_IO1
+ {PD_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P1_IO1
+ // {PE_4, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_IO1
+ // {PF_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO1
+ // {PG_1, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_IO1
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_OCTOSPI_DATA2[] = {
+ // {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO2
+ // {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P1_IO2
+ // {PE_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P1_IO2
+ // {PE_5, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_IO2
+ {PF_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO2
+ // {PG_2, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_IO2
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_OCTOSPI_DATA3[] = {
+ // {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P1_IO3
+ // {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPIM_P1_IO3
+ // {PA_9, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P2_IO3
+ {PD_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P1_IO3
+ // {PE_6, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_IO3
+ // {PF_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO3
+ // {PG_3, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_IO3
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_OCTOSPI_DATA4[] = {
+ // {PA_2, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_IO4
+ // {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO4
+ // {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO4
+ // {PD_6, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_IO4
+ {PE_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO4
+ // {PG_4, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_IO4
+ // {PG_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_OCTOSPI1)}, // OCTOSPIM_P1_IO4
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_OCTOSPI_DATA5[] = {
+ // {PA_5, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_IO5
+ // {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPIM_P1_IO5
+ {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO5
+ // {PE_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO5
+ // {PG_5, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_IO5
+ // {PG_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_OCTOSPI1)}, // OCTOSPIM_P1_IO5
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_OCTOSPI_DATA6[] = {
+ // {PA_15, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_IO6
+ // {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPIM_P1_IO6
+ {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO6
+ // {PE_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO6
+ // {PG_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P1_IO6
+ // {PG_10, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_IO6
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_OCTOSPI_DATA7[] = {
+ {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO7
+ // {PC_12, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_IO7
+ // {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO7
+ // {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO7
+ // {PG_14, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P1_IO7
+ // {PG_15, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_IO7
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_OCTOSPI_SCLK[] = {
+ // {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPIM_P1_CLK
+ // {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P1_CLK
+ // {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPIM_P1_CLK
+ // {PB_5, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P2_CLK
+ // {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_CLK
+ // {PD_14, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_CLK
+ // {PE_14, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_CLK
+ {PF_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P1_CLK
+ // {PG_7, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_CLK
+ // {PG_12, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_CLK
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_OCTOSPI_NCS1[] = {
+ // {PB_0, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_NCS1
+ // {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_NCS1
+ {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P1_NCS1
+ // {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P1_NCS1
+ // {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPIM_P1_NCS1
+ // {PE_15, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_NCS1
+ // {PG_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_NCS1
+ // {PG_6_ALT1, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_NCS1
+ // {PG_13, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_NCS1
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_OCTOSPI_NCS2[] = {
+ {PD_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_NCS2
+ // {PD_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P1_NCS2
+ // {PE_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_OCTOSPI1)}, // OCTOSPIM_P1_NCS2
+ // {PE_11, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_NCS2
+ // {PF_4, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_NCS2
+ // {PF_15, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_NCS2
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_OCTOSPI_NCLK[] = {
+ // {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P1_NCLK
+ {PB_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPIM_P1_NCLK
+ // {PB_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPIM_P1_NCLK
+ // {PD_15, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_NCLK
+ // {PF_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P1_NCLK
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_OCTOSPI_DQS[] = {
+ // {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPIM_P1_DQS
+ // {PA_8, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_DQS
+ {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_DQS
+ // {PC_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_DQS
+ // {PD_1, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P2_DQS
+ // {PF_5, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPIM_P2_DQS
+ {NC, NP, 0}
+};
+#endif
+
+//*** USB ***
+
+#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED)
+WEAK const PinMap PinMap_USB_OTG_FS[] = {
+ // {PA_8, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF_NONE)}, // USB_OTG_FS_SOF
+ // {PA_11, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF_NONE)}, // USB_OTG_FS_DM
+ // {PA_12, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF_NONE)}, // USB_OTG_FS_DP
+ {NC, NP, 0}
+};
+#endif
+
+#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED)
+WEAK const PinMap PinMap_USB_OTG_HS[] = {
+ {PA_4, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF_NONE)}, // USB_OTG_HS_SOF
+ {NC, NP, 0}
+};
+#endif
+
+//*** SD ***
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_CMD[] = {
+ {PA_0, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_SDMMC2)}, // SDMMC2_CMD
+ {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD
+ {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD
+ {PD_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF11_SDMMC2)}, // SDMMC2_CMD
+ {PF_15, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF8_SDMMC1)}, // SDMMC1_CMD
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_CK[] = {
+ // {PC_1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_SDMMC2)}, // SDMMC2_CK
+ {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF12_SDMMC1)}, // SDMMC1_CK
+ {PD_6, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF11_SDMMC2)}, // SDMMC2_CK
+ {PG_0, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF8_SDMMC1)}, // SDMMC1_CK
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_DATA0[] = {
+ {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0
+ {PD_8, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_SDMMC2)}, // SDMMC2_D0
+ {PF_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_SDMMC1)}, // SDMMC1_D0
+ {PG_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_SDMMC2)}, // SDMMC2_D0
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_DATA1[] = {
+ {PB_15, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_SDMMC2)}, // SDMMC2_D1
+ {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1
+ {PF_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_SDMMC1)}, // SDMMC1_D1
+ {PG_10, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_SDMMC2)}, // SDMMC2_D1
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_DATA2[] = {
+ {PB_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_SDMMC2)}, // SDMMC2_D2
+ {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2
+ // {PF_0, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_SDMMC2)}, // SDMMC2_D2
+ {PF_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_SDMMC1)}, // SDMMC1_D2
+ {PG_11, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_SDMMC2)}, // SDMMC2_D2
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_DATA3[] = {
+ {PB_4, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_SDMMC2)}, // SDMMC2_D3
+ {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3
+ {PF_1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_SDMMC2)}, // SDMMC2_D3
+ {PF_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_SDMMC1)}, // SDMMC1_D3
+ // {PG_12, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_SDMMC2)}, // SDMMC2_D3
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_DATA4[] = {
+ {PA_12, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_SDMMC2)}, // SDMMC2_D4
+ // {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4
+ // {PB_8_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_SDMMC2)}, // SDMMC2_D4
+ {PF_2, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_SDMMC2)}, // SDMMC2_D4
+ {PF_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_SDMMC1)}, // SDMMC1_D4
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_DATA5[] = {
+ {PB_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5
+ // {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5
+ // {PB_9_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5
+ {PF_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5
+ {PF_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_SDMMC1)}, // SDMMC1_D5
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_DATA6[] = {
+ {PC_2, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_SDMMC2)}, // SDMMC2_D6
+ {PF_4, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_SDMMC2)}, // SDMMC2_D6
+ {PF_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_SDMMC1)}, // SDMMC1_D6
+ {PG_13, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_SDMMC2)}, // SDMMC2_D6
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_DATA7[] = {
+ {PC_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_SDMMC2)}, // SDMMC2_D7
+ {PF_5, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_SDMMC2)}, // SDMMC2_D7
+ {PF_14, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_SDMMC1)}, // SDMMC1_D7
+ {PG_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_SDMMC2)}, // SDMMC2_D7
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_CKIN[] = {
+ {PB_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF11_SDMMC2)}, // SDMMC2_CKIN
+ // {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN
+ // {PB_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF11_SDMMC2)}, // SDMMC2_CKIN
+ {PF_5, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF11_SDMMC2)}, // SDMMC2_CKIN
+ {PF_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_SDMMC1)}, // SDMMC1_CKIN
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_CDIR[] = {
+ // {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF7_SDMMC1)}, // SDMMC1_CDIR
+ {PF_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_SDMMC1)}, // SDMMC1_CDIR
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_D0DIR[] = {
+ {PD_0, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF7_SDMMC1)}, // SDMMC1_D0DIR
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_D123DIR[] = {
+ // {PD_1, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF7_SDMMC1)}, // SDMMC1_D123DIR
+ {PF_14, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_SDMMC1)}, // SDMMC1_D123DIR
+ {NC, NP, 0}
+};
+#endif
+
+#endif /* ARDUINO_NUCLEO_H5E5ZJ */
diff --git a/variants/STM32H5xx/H5E5Z(J-K)T_H5F5ZJT/generic_clock.c b/variants/STM32H5xx/H5E5Z(J-K)T_H5F5ZJT/generic_clock.c
index 4afe785def..e068d3cec1 100644
--- a/variants/STM32H5xx/H5E5Z(J-K)T_H5F5ZJT/generic_clock.c
+++ b/variants/STM32H5xx/H5E5Z(J-K)T_H5F5ZJT/generic_clock.c
@@ -21,8 +21,92 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
+
+ while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI
+ | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_CSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV2;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+ RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ RCC_OscInitStruct.CSIState = RCC_CSI_ON;
+ RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI;
+ RCC_OscInitStruct.PLL.PLLM = 1;
+ RCC_OscInitStruct.PLL.PLLN = 125;
+ RCC_OscInitStruct.PLL.PLLP = 2;
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2;
+ RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;
+ RCC_OscInitStruct.PLL.PLLFRACN = 0;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
+ | RCC_CLOCKTYPE_PCLK3;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Configure the programming delay
+ */
+ __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2);
+
+
+ /** Initializes the peripherals clock
+ */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1
+#if defined(USBCON)
+#if defined(USE_USB_HS)
+#warning "USB HS is not supported with the default 'SystemClock_Config', please configure it manually."
+#else
+ | RCC_PERIPHCLK_USB
+#endif
+#endif
+ ;
+ PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
+#if defined(USBCON) && !defined(USE_USB_HS)
+ PeriphClkInitStruct.OtgfsClockSelection = RCC_OTGFSCLKSOURCE_HSI48;
+#endif
+ PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI;
+ PeriphClkInitStruct.PLL2.PLL2M = 1;
+ PeriphClkInitStruct.PLL2.PLL2N = 125;
+ PeriphClkInitStruct.PLL2.PLL2P = 2;
+ PeriphClkInitStruct.PLL2.PLL2Q = 2;
+ PeriphClkInitStruct.PLL2.PLL2R = 4;
+ PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2;
+ PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE;
+ PeriphClkInitStruct.PLL2.PLL2FRACN = 0.0;
+ PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVR;
+ PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R;
+ PeriphClkInitStruct.DacLowPowerClockSelection = RCC_DACLPCLKSOURCE_LSI;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32H5xx/H5E5Z(J-K)T_H5F5ZJT/ldscript.ld b/variants/STM32H5xx/H5E5Z(J-K)T_H5F5ZJT/ldscript.ld
new file mode 100644
index 0000000000..4ed1d3fc68
--- /dev/null
+++ b/variants/STM32H5xx/H5E5Z(J-K)T_H5F5ZJT/ldscript.ld
@@ -0,0 +1,189 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32H5E5ZJTx Device from STM32H5 series
+** 4096KBytes FLASH
+** 1536KBytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2026 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+_sstack = _estack - _Min_Stack_Size;
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ FLASH (rx) : ORIGIN = 0x08000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32H5xx/H5E5Z(J-K)T_H5F5ZJT/variant_NUCLEO_H5E5ZJ.cpp b/variants/STM32H5xx/H5E5Z(J-K)T_H5F5ZJT/variant_NUCLEO_H5E5ZJ.cpp
new file mode 100644
index 0000000000..1ae838fe2c
--- /dev/null
+++ b/variants/STM32H5xx/H5E5Z(J-K)T_H5F5ZJT/variant_NUCLEO_H5E5ZJ.cpp
@@ -0,0 +1,251 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020-2026, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#if defined(ARDUINO_NUCLEO_H5E5ZJ)
+#include "pins_arduino.h"
+
+// Digital PinName array
+const PinName digitalPin[] = {
+ PA_8, //D0
+ PB_4, //D1
+ PA_10, //D2
+ PF_1, //D3
+ PD_3, //D4
+ PG_15, //D5
+ PF_3, //D6
+ PE_9, //D7/A6
+ PA_9, //D8
+ PF_4, //D9
+ PE_11, //D10/A7
+ PE_14, //D11/A8
+ PE_13, //D12/A9
+ PE_12, //D13/A10
+ PG_6, //D14
+ PF_5, //D15
+ PA_6, //D16/A0
+ PA_7, //D17/A1
+ PA_4, //D18/A2
+ PB_0, //D19/A3
+ PF_12, //D20/A4
+ PF_11, //D21/A5
+ PA_3, //D22
+ PF_0, //D23
+ PE_5, //D24
+ PC_13, //D25
+ PD_8, //D26
+ PD_9, //D27
+ PA_1, //D28
+ PA_2, //D29
+ PC_1, //D30
+ PD_1, //D31
+ PC_4, //D32
+ PC_5, //D33
+ PA_5, //D34
+ PB_12, //D35
+ PG_12, //D36
+ PD_4, //D37
+ PB_13, //D38
+ PB_14, //D39
+ PA_11, //D40
+ PB_8, //D41
+ PB_9, //D42
+ PD_7, //D43
+ PG_9, //D44
+ PG_10, //D45
+ PB_2, //D46
+ PC_0, //D47
+ PE_7, //D48
+ PD_12, //D49
+ PD_11, //D50
+ PF_10, //D51
+ PB_5, //D52
+ PD_6, //D53
+ PD_5, //D54
+ PD_13, //D55
+ PF_7, //D56
+ PG_11, //D57
+ PG_5, //D58
+ PB_10, //D59
+ PD_0, //D60
+ PB_7, //D61
+ PB_6, //D62
+ PG_13, //D63
+ PC_10, //D64
+ PC_12, //D65
+ PG_0, //D66
+ PB_3, //D67
+ PA_13, //D68
+ PA_14, //D69
+ PA_15, //D70
+ PG_2, //D71
+ PA_0, //D72/A11
+ PC_14, //D73
+ PC_15, //D74
+ PH_0, //D75
+ PH_1, //D76
+ PC_2, //D77/A12
+ PC_3, //D78/A13
+ PC_11, //D79
+ PF_15, //D80
+ PG_1, //D81
+ PG_4, //D82
+ PC_9, //D83
+ PF_6, //D84
+ PD_14, //D85
+ PD_15, //D86
+ PE_0, //D87
+ PE_15, //D88/A14
+ PB_1, //D89/A15
+ PF_2, //D90
+ PF_14, //D91/A16
+ PB_15, //D92
+ PE_10, //D93/A17
+ PE_8, //D94/A18
+ PF_13, //D95/A19
+ PF_8, //D96
+ PF_9, //D97
+ PG_3, //D98
+ PD_10, //D99
+ PE_4, //D100
+ PG_7 //D101
+
+};
+
+// Analog (Ax) pin number array
+const pin_size_t analogInputPin[] = {
+ 16, // A0, PA6
+ 17, // A1, PA7
+ 18, // A2, PA4
+ 19, // A3, PB0
+ 20, // A4, PF12
+ 21, // A5, PF11
+ 7, // A6, PE9
+ 10, // A7, PE11
+ 11, // A8, PE14
+ 12, // A9, PE13
+ 13, // A10, PE12
+ 72, // A11, PA0
+ 77, // A12, PC2
+ 78, // A13, PC3
+ 88, // A14, PE15
+ 89, // A15, PB1
+ 91, // A16, PF14
+ 93, // A17, PE10
+ 94, // A18, PE8
+ 95 // A19, PF13
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief System Clock Configuration
+ * @param None
+ * @retval None
+ */
+WEAK void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
+
+ while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+
+ /** Configure LSE Drive Capability
+ * Warning : Only applied when the LSE is disabled.
+ */
+ HAL_PWR_EnableBkUpAccess();
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 3;
+ RCC_OscInitStruct.PLL.PLLN = 31;
+ RCC_OscInitStruct.PLL.PLLP = 2;
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_3;
+ RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;
+ RCC_OscInitStruct.PLL.PLLFRACN = 0;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
+ | RCC_CLOCKTYPE_PCLK3;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Configure the programming delay
+ */
+ __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2);
+
+ /** Initializes the peripherals clock
+ */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1
+ | RCC_PERIPHCLK_OTGHS;
+ PeriphClkInitStruct.OtghsClockSelection = RCC_OTGHSCLKSOURCE_HSE_DIV2;
+
+ PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE;
+ PeriphClkInitStruct.PLL2.PLL2M = 3;
+ PeriphClkInitStruct.PLL2.PLL2N = 31;
+ PeriphClkInitStruct.PLL2.PLL2P = 2;
+ PeriphClkInitStruct.PLL2.PLL2Q = 2;
+ PeriphClkInitStruct.PLL2.PLL2R = 4;
+ PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_3;
+ PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE;
+ PeriphClkInitStruct.PLL2.PLL2FRACN = 0.0;
+ PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVR;
+ PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R;
+ PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_HSE;
+ PeriphClkInitStruct.PLL3.PLL3M = 3;
+ PeriphClkInitStruct.PLL3.PLL3N = 31;
+ PeriphClkInitStruct.PLL3.PLL3P = 2;
+ PeriphClkInitStruct.PLL3.PLL3Q = 16;
+ PeriphClkInitStruct.PLL3.PLL3R = 2;
+ PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_3;
+ PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE;
+ PeriphClkInitStruct.PLL3.PLL3FRACN = 0.0;
+ PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ;
+ PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL3Q;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+ /* Configure desired clock settings for OTG_HS PHY */
+ __HAL_RCC_OTGPHY_CONFIG(RCC_OTGPHYREFCKCLKSOURCE_24M);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ARDUINO_NUCLEO_H5E5ZJ */
diff --git a/variants/STM32H5xx/H5E5Z(J-K)T_H5F5ZJT/variant_NUCLEO_H5E5ZJ.h b/variants/STM32H5xx/H5E5Z(J-K)T_H5F5ZJT/variant_NUCLEO_H5E5ZJ.h
new file mode 100644
index 0000000000..599e44128c
--- /dev/null
+++ b/variants/STM32H5xx/H5E5Z(J-K)T_H5F5ZJT/variant_NUCLEO_H5E5ZJ.h
@@ -0,0 +1,366 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020-2026, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#pragma once
+
+/*----------------------------------------------------------------------------
+ * STM32 pins number
+ *----------------------------------------------------------------------------*/
+// ARDUINO® Uno V3 connectors
+// CN9
+#define PA8 0
+#define PB4 1
+#define PA10 2
+#define PF1 3
+#define PD3 4
+#define PG15 5
+#define PF3 6
+#define PE9 PIN_A6
+// CN5
+#define PA9 8
+#define PF4 9
+#define PE11 PIN_A7
+#define PE14 PIN_A8
+#define PE13 PIN_A9
+#define PE12 PIN_A10
+#define PG6 14
+#define PF5 15
+// CN8
+#define PA6 PIN_A0
+#define PA7 PIN_A1
+#define PA4 PIN_A2
+#define PB0 PIN_A3
+#define PF12 PIN_A4
+#define PF11 PIN_A5
+// Dedicated pins
+#define PA3 22 // LED green
+#define PF0 23 // LED red
+#define PE5 24 // LED blue
+#define PC13 25 // User button
+#define PD8 26 // USART3 Tx
+#define PD9 27 // USART3 Rx
+// Ethernet
+#define PA1 28
+#define PA2 29
+#define PC1 30
+#define PD1 31
+#define PC4 32
+#define PC5 33
+#define PA5 34
+#define PB12 35
+#define PG12 36
+#define PD4 37
+// UCPD
+#define PB13 38
+#define PB14 39
+#define PA11 40
+#define PB8 41
+#define PB9 42
+// CN19 M.2 Key A connector
+// Odd pins of the M.2 Key A connector
+#define PD7 43
+#define PG9 44
+#define PG10 45
+#define PB2 46
+#define PC0 47
+#define PE7 48
+#define PD12 49
+#define PD11 50
+#define PF10 51
+#define PB5 52
+// PC0
+#define PD6 53
+#define PD5 54
+// PE7
+#define PD13 55
+#define PF7 56
+// PD12
+// PD11
+// PF10
+// PB5
+// Even pins of the M.2 Key A connector
+#define PG11 57
+#define PG5 58
+#define PB10 59
+#define PD0 60
+// PD6
+// PD5
+// PD13
+// PF7
+// PD0
+// PB2
+#define PB7 61
+#define PB6 62
+#define PG13 63
+// CN7 ST morpho connector
+// Odd pins of the ST morpho connector
+#define PC10 64
+#define PC12 65
+#define PG0 66
+#define PB3 67
+#define PA13 68
+#define PA14 69
+#define PA15 70
+#define PG2 71
+#define PA0 PIN_A11
+#define PC14 73
+#define PC15 74
+#define PH0 75
+#define PH1 76
+#define PC2 PIN_A12
+#define PC3 PIN_A13
+// Even pins of the ST morpho connector
+#define PC11 79
+#define PF15 80
+#define PG1 81
+#define PG4 82
+// Shared pin with the ARDUINO® Uno V3 connector.
+// PA6
+// PA7
+// PA4
+// PB0
+// PF12
+// PF11
+// CN10 ST morpho connector
+// Odd pins of the CN10 ST morpho connector
+#define PC9 83
+// Shared pin with the ARDUINO® Uno V3 connector.
+// PF5
+// PG6
+// PE12
+// PE13
+// PE14
+// PE11
+// PF4
+// PA9
+// PE9
+// PF3
+// PG15
+// PD3
+// PF1
+// PA10
+// PB4
+// PA8
+// Even pins of the CN10 ST morpho connector
+#define PF6 84
+#define PD14 85
+#define PD15 86
+#define PE0 87
+#define PE15 PIN_A14
+#define PB1 PIN_A15
+#define PF2 90
+#define PF14 PIN_A16
+#define PB15 92
+#define PE10 PIN_A17
+#define PE8 PIN_A18
+#define PF13 PIN_A19
+#define PF8 96
+#define PF9 97
+// CN11 expansion connector
+// Most of pins already defined for the M.2 key A connector
+// Odd pins of the CN11 expansion connector
+// PD11
+// PD12
+// PF7
+// PD13
+// PE7
+// PD5
+// PD6
+// PC0
+// PB10
+// PD0
+// PB2
+// PF10
+// PB5
+// CN12 ST morpho connector
+// Odd pins of the CN12 ST morpho connector
+// PB7
+// PB6
+// PG5
+// PG13
+// Even pins of the CN12 ST morpho connector
+// PG10
+// PG11
+// PG9
+// PD7
+#define PG3 98
+#define PD10 99
+#define PE4 100
+#define PG7 101
+// TRACE
+// PE2
+// PE3
+// PG14
+// PD2
+// PE6
+// Not connected
+// PA12
+
+
+// Alternate pins number
+#define PA0_ALT1 (PA0 | ALT1)
+#define PA1_ALT1 (PA1 | ALT1)
+#define PA1_ALT2 (PA1 | ALT2)
+#define PA2_ALT1 (PA2 | ALT1)
+#define PA2_ALT2 (PA2 | ALT2)
+#define PA3_ALT1 (PA3 | ALT1)
+#define PA3_ALT2 (PA3 | ALT2)
+#define PA4_ALT1 (PA4 | ALT1)
+#define PA4_ALT2 (PA4 | ALT2)
+#define PA5_ALT1 (PA5 | ALT1)
+#define PA6_ALT1 (PA6 | ALT1)
+#define PA7_ALT1 (PA7 | ALT1)
+#define PA7_ALT2 (PA7 | ALT2)
+#define PA7_ALT3 (PA7 | ALT3)
+#define PA9_ALT1 (PA9 | ALT1)
+#define PA10_ALT1 (PA10 | ALT1)
+#define PA11_ALT1 (PA11 | ALT1)
+#define PA12_ALT1 (PA12 | ALT1)
+#define PA15_ALT1 (PA15 | ALT1)
+#define PA15_ALT2 (PA15 | ALT2)
+#define PB0_ALT1 (PB0 | ALT1)
+#define PB0_ALT2 (PB0 | ALT2)
+#define PB1_ALT1 (PB1 | ALT1)
+#define PB1_ALT2 (PB1 | ALT2)
+#define PB2_ALT1 (PB2 | ALT1)
+#define PB3_ALT1 (PB3 | ALT1)
+#define PB3_ALT2 (PB3 | ALT2)
+#define PB4_ALT1 (PB4 | ALT1)
+#define PB4_ALT2 (PB4 | ALT2)
+#define PB5_ALT1 (PB5 | ALT1)
+#define PB5_ALT2 (PB5 | ALT2)
+#define PB6_ALT1 (PB6 | ALT1)
+#define PB6_ALT2 (PB6 | ALT2)
+#define PB7_ALT1 (PB7 | ALT1)
+#define PB8_ALT1 (PB8 | ALT1)
+#define PB9_ALT1 (PB9 | ALT1)
+#define PB12_ALT1 (PB12 | ALT1)
+#define PB14_ALT1 (PB14 | ALT1)
+#define PB14_ALT2 (PB14 | ALT2)
+#define PB15_ALT1 (PB15 | ALT1)
+#define PB15_ALT2 (PB15 | ALT2)
+#define PC0_ALT1 (PC0 | ALT1)
+#define PC1_ALT1 (PC1 | ALT1)
+#define PC2_ALT1 (PC2 | ALT1)
+#define PC2_ALT2 (PC2 | ALT2)
+#define PC3_ALT1 (PC3 | ALT1)
+#define PC4_ALT1 (PC4 | ALT1)
+#define PC5_ALT1 (PC5 | ALT1)
+#define PC9_ALT1 (PC9 | ALT1)
+#define PC10_ALT1 (PC10 | ALT1)
+#define PC11_ALT1 (PC11 | ALT1)
+#define PD1_ALT1 (PD1 | ALT1)
+#define PD8_ALT1 (PD8 | ALT1)
+#define PD13_ALT1 (PD13 | ALT1)
+#define PE4_ALT1 (PE4 | ALT1)
+#define PE5_ALT1 (PE5 | ALT1)
+#define PE7_ALT1 (PE7 | ALT1)
+#define PE8_ALT1 (PE8 | ALT1)
+#define PE11_ALT1 (PE11 | ALT1)
+#define PF8_ALT1 (PF8 | ALT1)
+#define PF9_ALT1 (PF9 | ALT1)
+#define PG6_ALT1 (PG6 | ALT1)
+#define PG9_ALT1 (PG9 | ALT1)
+#define PG11_ALT1 (PG11 | ALT1)
+#define PG12_ALT1 (PG12 | ALT1)
+#define PG13_ALT1 (PG13 | ALT1)
+#define PG14_ALT1 (PG14 | ALT1)
+
+#define NUM_DIGITAL_PINS 102
+#define NUM_ANALOG_INPUTS 20
+
+// On-board LED pin number
+#define LED_GREEN PA3 // active HIGH
+#define LED_RED PF0 // active LOW
+#define LED_BLUE PE5 // active HIGH
+#ifndef LED_BUILTIN
+ #define LED_BUILTIN LED_GREEN
+#endif
+
+// On-board user button
+#ifndef USER_BTN
+ #define USER_BTN PC13 // active HIGH
+#endif
+
+// Timer Definitions
+// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin
+#ifndef TIMER_TONE
+ #define TIMER_TONE TIM6
+#endif
+#ifndef TIMER_SERVO
+ #define TIMER_SERVO TIM7
+#endif
+
+// UART Definitions
+#ifndef SERIAL_UART_INSTANCE
+ #define SERIAL_UART_INSTANCE 3
+#endif
+
+// Default pin used for generic 'Serial' instance
+// Mandatory for Firmata
+#ifndef PIN_SERIAL_RX
+ #define PIN_SERIAL_RX PD9
+#endif
+#ifndef PIN_SERIAL_TX
+ #define PIN_SERIAL_TX PD8
+#endif
+
+// Extra HAL modules
+#if !defined(HAL_DAC_MODULE_DISABLED)
+ #define HAL_DAC_MODULE_ENABLED
+#endif
+#if !defined(HAL_ETH_MODULE_DISABLED)
+ #define HAL_ETH_MODULE_ENABLED
+#endif
+#if !defined(HAL_I3C_MODULE_DISABLED)
+ #define HAL_I3C_MODULE_ENABLED
+#endif
+#if !defined(HAL_OSPI_MODULE_DISABLED)
+ #define HAL_OSPI_MODULE_ENABLED
+#endif
+#if !defined(HAL_SD_MODULE_DISABLED)
+ #define HAL_SD_MODULE_ENABLED
+#endif
+
+// Value of the External oscillator in Hz
+#define HSE_VALUE 48000000UL
+
+// Pin UCPD to configure TCPP in default Type-C legacy state (UCPD_DBn for TCPP01)
+#define PIN_UCPD_TCPP PB9
+
+/*----------------------------------------------------------------------------
+ * Arduino objects - C++ only
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ // These serial port names are intended to allow libraries and architecture-neutral
+ // sketches to automatically default to the correct port name for a particular type
+ // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN,
+ // the first hardware serial port whose RX/TX pins are not dedicated to another use.
+ //
+ // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor
+ //
+ // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial
+ //
+ // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library
+ //
+ // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins.
+ //
+ // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX
+ // pins are NOT connected to anything by default.
+ #ifndef SERIAL_PORT_MONITOR
+ #define SERIAL_PORT_MONITOR Serial
+ #endif
+ #ifndef SERIAL_PORT_HARDWARE
+ #define SERIAL_PORT_HARDWARE Serial
+ #endif
+#endif