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1. 32-bit-multicycle-mips-cpu 32-bit-multicycle-mips-cpu Public

   Synthesizable 32-bit multi-cycle MIPS processor core in Verilog HDL featuring an FSM controller, unified memory architecture, and verified on Xilinx Artix-7 FPGA using Vivado.

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2. verilog-alu-project verilog-alu-project Public

   Parametric N-bit Arithmetic Logic Unit (ALU) supporting arithmetic, logical, shift, and comparison operations with real-time status flag generation in Verilog HDL.

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3. Intelligent-Traffic-Light-Controller Intelligent-Traffic-Light-Controller Public

   FSM-based Intelligent Traffic Light Controller designed and verified using Verilog HDL with adaptive signal timing, pedestrian support, emergency vehicle priority, and night mode operation.

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