net: macb: add RP1 PHC GPIO timestamp input and PPS output

Documentation/devicetree/bindings/net/cdns,macb.yaml

@@ -39,6 +39,10 @@ properties:
               - microchip,mpfs-macb   # Microchip PolarFire SoC
           - const: cdns,macb          # Generic
 
+      - items:
+          - const: raspberrypi,rp1-gem # Raspberry Pi RP1 gigabit ethernet interface
+          - const: cdns,macb           # Generic
+
       - items:
           - enum:
               - atmel,sama5d3-macb    # 10/100Mbit IP on Atmel sama5d3 SoCs
@@ -70,7 +74,13 @@ properties:
     minItems: 1
     items:
       - description: Basic register set
-      - description: GEMGXL Management block registers on SiFive FU540-C000 SoC
+      - description: SoC-specific auxiliary register set
+
+  reg-names:
+    minItems: 1
+    items:
+      - const: macb
+      - enum: [gemxl_mgmt, eth_cfg]
 
   interrupts:
     minItems: 1
@@ -87,7 +97,7 @@ properties:
       - enum: [ ether_clk, hclk, pclk ]
       - enum: [ hclk, pclk ]
       - enum: [ tx_clk, tsu_clk ]
-      - enum: [ rx_clk, tsu_clk ]
+      - enum: [ rx_clk, tx_clk, tsu_clk ]
       - const: tsu_clk
 
   local-mac-address: true
@@ -96,6 +106,26 @@ properties:
 
   phy-handle: true
 
+  raspberrypi,pio:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      RP1 PIO provider used for Ethernet PTP GPIO timestamping and output.
+
+  raspberrypi,gpio-controller:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      RP1 GPIO provider used to reserve and route PTP-capable pins.
+
+  phy-reset-gpios:
+    maxItems: 1
+    deprecated: true
+    description: GPIO used to reset the Ethernet PHY.
+
+  phy-reset-duration:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    deprecated: true
+    description: PHY reset duration in milliseconds.
+
   phys:
     maxItems: 1
 
@@ -146,12 +176,16 @@ properties:
       be direct children.
 
   cdns,aw2w-max-pipe:
-    $ref: /schemas/types.yaml#/definitions/uint32
+    oneOf:
+      - $ref: /schemas/types.yaml#/definitions/uint32
+      - $ref: /schemas/types.yaml#/definitions/uint8
     description:
       Maximum number of outstanding AXI write requests
 
   cdns,ar2r-max-pipe:
-    $ref: /schemas/types.yaml#/definitions/uint32
+    oneOf:
+      - $ref: /schemas/types.yaml#/definitions/uint32
+      - $ref: /schemas/types.yaml#/definitions/uint8
     description:
       Maximum number of outstanding AXI read requests
 
@@ -169,6 +203,19 @@ patternProperties:
     properties:
       reset-gpios: true
 
+      brcm,powerdown-enable:
+        type: boolean
+        description:
+          Allow the Broadcom PHY to enter its low-power mode when the link is
+          down.
+
+      led-modes:
+        $ref: /schemas/types.yaml#/definitions/uint32-array
+        minItems: 2
+        maxItems: 2
+        description:
+          Broadcom PHY LED mode values for the two integrated LED outputs.
+
       magic-packet:
         type: boolean
         deprecated: true
@@ -189,15 +236,40 @@ allOf:
   - $ref: ethernet-controller.yaml#
 
   - if:
-      not:
-        properties:
-          compatible:
-            contains:
-              const: sifive,fu540-c000-gem
+      properties:
+        compatible:
+          contains:
+            const: raspberrypi,rp1-gem
     then:
       properties:
         reg:
-          maxItems: 1
+          minItems: 2
+          maxItems: 2
+        reg-names:
+          items:
+            - const: macb
+            - const: eth_cfg
+        clock-names:
+          items:
+            - const: pclk
+            - const: hclk
+            - const: tsu_clk
+            - const: tx_clk
+      required:
+        - reg-names
+        - raspberrypi,pio
+        - raspberrypi,gpio-controller
+    else:
+      if:
+        not:
+          properties:
+            compatible:
+              contains:
+                const: sifive,fu540-c000-gem
+      then:
+        properties:
+          reg:
+            maxItems: 1
 
 unevaluatedProperties: false
 

Documentation/networking/device_drivers/ethernet/cadence/macb-rp1-ptp.rst

@@ -0,0 +1,104 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+=============================
+RP1 Ethernet PTP GPIO support
+=============================
+
+The Raspberry Pi RP1 Ethernet controller exposes its Precision Time Protocol
+hardware clock (PHC) through the standard Linux PTP device interface. With
+``CONFIG_MACB_RP1_PPS`` enabled, the driver also exposes RP1 GPIO pins for
+external timestamp input and periodic output. Applications use the standard
+PTP clock ioctls; no private userspace interface is added.
+
+The driver advertises GPIO0 through GPIO27 as PTP pins. Select an RP1 GPIO
+number, not a 40-pin header pin number. Pin reservation is checked when a
+channel is enabled. A pin in use by another peripheral or GPIO interrupt is
+rejected. Board wiring and other pin users can make a listed pin unavailable.
+This PHC interface is separate from the ``pps-rp1`` overlay, which configures
+the LinuxPPS ``pps-gpio`` driver. Do not configure both interfaces on the same
+GPIO.
+
+The implementation provides two external timestamp channels and one periodic
+output channel. Without PEROUT, channel 0 uses the Ethernet timestamp latch;
+channel 1 requires PEROUT to supply a PHC anchor. With PEROUT active, both
+EXTTS channels use separate RP1 PIO counter and DMA lanes, and each input must
+use a GPIO different from the output GPIO and from the other input GPIO. The
+simultaneous counter path currently supports rising edges only. Stop channel 1
+before disabling PEROUT. Channel 0 returns to direct latch capture when PEROUT
+is stopped.
+
+Periodic output supports a 1-second period. The default output pulse is high
+for 500 ms. A duty-cycle request can select a high time from 1 ms through
+500 ms, in 5 ns increments. These are hardware programming increments, not a
+statement of physical pin accuracy. Counter-derived input timestamps are
+mapped into the PHC domain from output-pad monitor samples and PEROUT TSU
+markers. The mapping has not been electrically calibrated, so it does not
+establish a board-level accuracy bound.
+
+Discover the PHC and the pin table first. The PHC device number may change
+between boots or driver registration:
+
+.. code-block:: sh
+
+   sudo testptp -d /dev/ptpN -c
+   sudo testptp -d /dev/ptpN -l
+
+For rising-edge input on GPIO18 on channel 0, map the pin to the external
+timestamp function, then request events. ``testptp`` disables the capture
+request after reading the requested number of events:
+
+.. code-block:: sh
+
+   sudo testptp -d /dev/ptpN -i 0 -L 18,1
+   sudo testptp -d /dev/ptpN -i 0 -E 1 -e 8
+
+Channel 0 direct capture also accepts ``-E 2`` for falling edges and ``-E 3``
+for both edges. The PTP channel index is selected with ``-i``. The mapping can
+be cleared with ``-L 18,0``.
+
+For 1 Hz output on GPIO23 with a 10 ms high pulse:
+
+.. code-block:: sh
+
+   sudo testptp -d /dev/ptpN -i 0 -L 23,2
+   sudo testptp -d /dev/ptpN -i 0 -p 1000000000 -w 10000000
+
+For simultaneous output and two rising-edge inputs, map three distinct GPIOs.
+Enable PEROUT first, then start one capture process per EXTTS channel:
+
+.. code-block:: sh
+
+   sudo testptp -d /dev/ptpN -i 0 -L 23,2
+   sudo testptp -d /dev/ptpN -i 0 -L 18,1
+   sudo testptp -d /dev/ptpN -i 1 -L 24,1
+   sudo testptp -d /dev/ptpN -i 0 -p 1000000000 -w 10000000
+   sudo testptp -d /dev/ptpN -i 0 -E 1 -e 8
+   sudo testptp -d /dev/ptpN -i 1 -E 1 -e 8
+
+Disable input mappings before stopping PEROUT. The channel-1 mapping and
+capture depend on active output markers:
+
+.. code-block:: sh
+
+   sudo testptp -d /dev/ptpN -i 1 -L 24,0
+   sudo testptp -d /dev/ptpN -i 0 -L 18,0
+   sudo testptp -d /dev/ptpN -i 0 -p 0
+   sudo testptp -d /dev/ptpN -i 0 -L 23,0
+
+The output request remains enabled after ``testptp`` exits. Disable it
+explicitly before changing the pin mapping or removing the Ethernet device:
+
+.. code-block:: sh
+
+   sudo testptp -d /dev/ptpN -i 0 -p 0
+   sudo testptp -d /dev/ptpN -i 0 -L 23,0
+
+Add ``-H <nanoseconds>`` to request a phase within the 1-second period. The
+output is aligned to the PHC, but physical pin delay and jitter have not been
+specified by this interface. PHC time steps temporarily inhibit output while
+the driver re-establishes the requested phase grid.
+
+The driver creates diagnostic counters under debugfs when it is enabled. They
+report capture collection age, input re-arm dead time, output latch error and
+frequency-change handling. Debugfs records are diagnostic measurements, not a
+calibration certificate or an accuracy guarantee.

Documentation/networking/device_drivers/ethernet/index.rst

@@ -18,6 +18,7 @@ Contents:
    amd/pds_vdpa
    amd/pds_vfio_pci
    aquantia/atlantic
+   cadence/macb-rp1-ptp
    chelsio/cxgb
    cirrus/cs89x0
    dlink/dl2k

arch/arm64/boot/dts/broadcom/rp1.dtsi

@@ -997,8 +997,12 @@
 		};
 
 		rp1_eth: ethernet@100000 {
-			reg = <0xc0 0x40100000  0x0 0x4000>;
+			reg = <0xc0 0x40100000  0x0 0x4000>,
+			      <0xc0 0x40104000  0x0 0x4000>;
+			reg-names = "macb", "eth_cfg";
 			compatible = "raspberrypi,rp1-gem", "cdns,macb";
+			raspberrypi,pio = <&rp1_pio>;
+			raspberrypi,gpio-controller = <&rp1_gpio>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <RP1_INT_ETH IRQ_TYPE_LEVEL_HIGH>;

arch/arm64/configs/bcm2712_defconfig

@@ -458,7 +458,7 @@ CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_BRCMSTB_GISB_ARB is not set
 CONFIG_RASPBERRYPI_FIRMWARE=y
-CONFIG_FIRMWARE_RP1=m
+CONFIG_FIRMWARE_RP1=y
 # CONFIG_EFI_VARS_PSTORE is not set
 CONFIG_MTD=m
 CONFIG_MTD_BLOCK=m
@@ -482,7 +482,7 @@ CONFIG_ATA_OVER_ETH=m
 CONFIG_BLK_DEV_RBD=m
 CONFIG_BLK_DEV_NVME=y
 CONFIG_NVME_HWMON=y
-CONFIG_RP1_PIO=m
+CONFIG_RP1_PIO=y
 CONFIG_WS2812_PIO_RP1=m
 CONFIG_SRAM=y
 CONFIG_EEPROM_AT24=m
@@ -535,6 +535,7 @@ CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
 CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m
 CONFIG_BCMGENET=y
 CONFIG_MACB=y
+CONFIG_MACB_RP1_PPS=y
 CONFIG_IGB=m
 CONFIG_IXGBE=m
 CONFIG_I40E=m
@@ -1562,7 +1563,7 @@ CONFIG_COMMON_CLK_SI5351=m
 CONFIG_CLK_RASPBERRYPI=y
 CONFIG_MAILBOX=y
 CONFIG_BCM2835_MBOX=y
-CONFIG_MBOX_RP1=m
+CONFIG_MBOX_RP1=y
 CONFIG_BCM2712_IOMMU=y
 CONFIG_RASPBERRYPI_POWER=y
 CONFIG_IIO=m