cxl

FEMU: Accurate, Scalable and Extensible NVMe SSD Emulator (FAST'18)

A "device memory" enabling project encompassing tools and libraries for CXL, NVDIMMs, DAX, memory tiering and other platform memory device topics.

Pond: CXL-Based Memory Pooling Systems for Cloud Platforms (ASPLOS'23)

A full-system, cycle-level simulator based on gem5 that provides complete support for all three CXL sub-protocols and all three types of CXL devices.

Disaggregated filesystem for CXL and multikernel shared memory

A library for constructing allocators and memory pools. It also contains broadly useful abstractions and utilities for memory management. UMF allows users to manage multiple memory pools characterized by different attributes, allowing certain allocation types to be isolated from others and allocated using different hardware resources as required.

High-Performance KV Cache Storage Engine on CXL Shared Memory for LLM Inference

IBEX: Internal Bandwidth‑Efficient Compression Architecture for Scalable CXL Memory Expansion (ICS'26)

Tigon: A Distributed Database for a CXL Pod [OSDI '25]

[ACM CoNEXT22 Best Paper Award] NTSocks: An ultra-low latency and compatible PCIe interconnect for rack-scale disaggregation.

Tiered Memory Management Beyond Hotness (OSDI'25)

Pin based tool for simulation of rack-scale disaggregated memory systems

Hardware-accelerated Linux kernel block driver and multi-tier memory cascade (ZRAM ➔ PCIe VRAM ➔ NVMe). Opportunistically leases idle GPU memory as a zero-allocation, revocable swap cache with sub-millisecond latency, zero SSD wear, and crash-safety on Linux & WSL2.

CXL Management Interface library

Systematic CXL Memory Characterization and Performance Analysis at Scale (ASPLOS'25)

Contain some materials about CXL.

STREAMer: Benchmarking remote volatile and non-volatile memory bandwidth

kernel development code for my work (ioatdma, ntb_hw_intel, idxd, PCI, and CXL related bits)

Codes for our ADMS'24 paper "Bandwidth Expansion via CXL: A Pathway to Accelerating In-Memory Analytical Processing".

PACT: A Criticality-First Design for Tiered Memory (ASPLOS '26)