rv32

Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)

RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

RISC-V Assembler and Runtime Simulator

Simple risc-v emulator, able to run linux, written in C.

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

🎓 Instructional RISC-V processor design framework: single-cycle to 5-stage pipeline with FPGA verification and complete learning guidelines! A RISC-V CPU design guideline.

Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice

Single-file header-only immediate-mode TCP/IP stack geared for 32-bit embedded processors.

LZ4 decoder in assembly for RiscV RV32IC

RISC-V ISA emulator

Design guidelines and performance analysis for 10 RISC-V 5- to 8-stage pipeline variants based on basic_RV32S and IMA_make_RV64, covering ISA extension scaling, pipeline-depth sweep, and 100 MHz(125) timing closure on Artix-7 FPGA.

WIP RISC-V emulator written in Zig

Common types for assembly architectures

"DHRYSTONE" Benchmark Program by Reinhold P. Weicker. Forked from SiFive repository.

Stoic-V: a deterministic RV32IM + Zba/Zbb/Zbs + Zicsr (M-mode) RISC-V soft core in SystemVerilog. No caches, speculation, or branch prediction, so timing is operand-independent and WCET is statically analysable. Drop-in replacement for the AMD MicroBlaze-V via the LMB v10 interface; closes 250 MHz on UltraScale+.

VHDL_Lab Course

Heterogeneous streaming SoC — RV32IM CPU + NPU with MOESI coherency. RTL, testbenches, docs, and automation.

A 32-bit, RISC-V architecture based CPU

A project dedicated to building LLVM toolchain for 32-bit RISCV embedded targets.

Three RV32 CPU profiles: 5-stage performance, Sv32/Linux system, and 2-wide OoO, with Verilator/NEMU verification and Nangate45 academic ASIC evidence.