Fixed the RISC-V64 trap frame size mismatch in the regression test BSP

[fdesbiens]

The RISC-V64 port moved its interrupt frame to 528 bytes in #698 — 65 slots plus 8 bytes of padding, so sp stays 16-byte aligned at a call — and published the size as TX_RISCV_TRAP_FRAME_SIZE. The port sources were converted to consume it. The shared regression test BSP was not: trap_entry in test/tx/cmake/riscv/bsp/tx_initialize_low_level.S still allocates a hardcoded 65 * REGBYTES.

Disassembled from the current dev:

trap_entry (test BSP):          addi  sp,sp,-520
_tx_thread_context_restore:     addi  sp,sp,528     (x2)

Every interrupt unwinds 8 bytes more than it allocated.

The example BSP under the port directory was converted along with the port, which is why the QEMU functional target kept passing and this went unnoticed. The RISC-V regression jobs are commented out in regression_test.yml, so CI did not catch it either.

Measured effect

RISC-V64, default_build, 95 tests, QEMU. Each tree built with ninja -k 0 so that every linkable target is actually present — without that, missing binaries are counted as failures and the numbers are meaningless:

Tree	Failures
Before #698 (515ab8ab)	2
Current dev	24
With this change	2

This restores the suite exactly to its pre-#698 state. The failure signature was an illegal instruction (mcause=0x2) once execution reached a corrupted frame.

The two residual failures predate all of this and are unrelated: newlib pulls _impure_ptr out of R_RISCV_HI20 range for time(), so threadx_thread_delayed_suspension_test and threadx_thread_wait_abort_and_isr_test do not link. #691 addresses that with a local time() implementation.

The change

The test BSP now derives both frame sizes from the port it is linked against, so the two cannot drift apart again. A port that publishes no contract keeps the historical layout, so RISC-V32 is byte-identical until its own port publishes one.

TX_RISCV_TRAP_CALL_FRAME_SIZE is restored to the RISC-V64 tx_port.h. It was removed as unused when the frame sizes were introduced, but it belongs to the same contract — the space a trap entry reserves around a call into C, which the psABI requires to be 16 bytes rather than one register slot.

Verification

• RISC-V64 default_build: 24 → 2 failures, matching the pre-riscv64: spec compliance and regression test fix #698 baseline.
• RISC-V32, all five configurations: 2 failures before and after, the same two tests each time. No change.
• Emitted frame allocation confirmed by disassembly: RV64 trap_entry now addi sp,sp,-528; RV32 unchanged at -260.

Note on ordering

#691 was intended to land before #698. It is what teaches the shared BSP to consume the port contract, and it fixes the newlib time() link error. Merging #698 first left the shared BSP on the old hardcoded size against a port that had moved. This change supplies that missing groundwork for RISC-V64; #691 can then drop its now-redundant __riscv_xlen == 32 guard on the same include.