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Fixed the RISC-V64 trap frame size mismatch in the regression test BSP #708

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Merged
fdesbiens merged 1 commit into from
Sep 9, 2026
Merged

Fixed the RISC-V64 trap frame size mismatch in the regression test BSP #708

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5 changes: 5 additions & 0 deletions ports/risc-v64/gnu/inc/tx_port.h
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Original file line number Diff line number Diff line change
Expand Up @@ -84,6 +84,11 @@
#define TX_RISCV_TRAP_FRAME_SIZE 256
#endif

/* Bytes a trap entry reserves around a call into C. The RISC-V psABI
requires sp to stay 16-byte aligned at a call boundary, so this is 16
rather than one register slot. */
#define TX_RISCV_TRAP_CALL_FRAME_SIZE 16


#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
#define TX_RISCV_SOL_FRAME_SIZE 240
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33 changes: 26 additions & 7 deletions test/tx/cmake/riscv/bsp/tx_initialize_low_level.S
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Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
/***************************************************************************
* Copyright (c) 2026 10xEngineers
* Copyright (c) 2026 Eclipse ThreadX contributors
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
Expand All @@ -8,10 +9,13 @@
* SPDX-License-Identifier: MIT
**************************************************************************/

// Some portions generated by Claude Code (Opus 5).

/* Trap entry and low-level init for RISC-V QEMU virt regression tests.
Supports both RV32 and RV64 via __riscv_xlen conditionals. */

#include "csr.h"
#include "tx_port.h"

#if __riscv_xlen == 64
#define STORE sd
Expand All @@ -33,25 +37,40 @@
.extern trap_handler
.extern _tx_thread_context_restore

trap_entry:
/* Take the interrupt frame size from the port that this BSP is linked
against, so the two can never disagree. A port that publishes no
contract keeps the historical layout. */
#ifndef TX_RISCV_TRAP_FRAME_SIZE
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
addi sp, sp, -(65 * REGBYTES)
#define TX_RISCV_TRAP_FRAME_SIZE (65 * REGBYTES)
#else
addi sp, sp, -(32 * REGBYTES)
#define TX_RISCV_TRAP_FRAME_SIZE (32 * REGBYTES)
#endif
#endif

/* The RISC-V psABI requires sp to be 16-byte aligned at a call. */
#ifndef TX_RISCV_TRAP_CALL_FRAME_SIZE
#define TX_RISCV_TRAP_CALL_FRAME_SIZE 16
#endif

.equ TX_TRAP_FRAME_SIZE, TX_RISCV_TRAP_FRAME_SIZE
.equ TX_TRAP_CALL_FRAME_SIZE, TX_RISCV_TRAP_CALL_FRAME_SIZE

trap_entry:
addi sp, sp, -TX_TRAP_FRAME_SIZE

STORE x1, (28 * REGBYTES)(sp)

call _tx_thread_context_save

csrr a0, mcause
csrr a1, mepc
csrr a2, mtval
addi sp, sp, -REGBYTES
addi sp, sp, -TX_TRAP_CALL_FRAME_SIZE
STORE ra, 0(sp)
call trap_handler
LOAD ra, 0(sp)
addi sp, sp, REGBYTES
addi sp, sp, TX_TRAP_CALL_FRAME_SIZE

call _tx_thread_context_restore

Expand Down Expand Up @@ -89,11 +108,11 @@ _tx_initialize_low_level:
fscsr x0
#endif

addi sp, sp, -REGBYTES
addi sp, sp, -TX_TRAP_CALL_FRAME_SIZE
STORE ra, 0(sp)
call board_init
LOAD ra, 0(sp)
addi sp, sp, REGBYTES
addi sp, sp, TX_TRAP_CALL_FRAME_SIZE

la t0, trap_entry
csrw mtvec, t0
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